Commit Graph

4 Commits

Author SHA1 Message Date
2a03cb1145 jtag/fpga: prog method tag + RTCK link setting (phase C)
- fpga_target gains a prog method (proxy_spi/svf/none), set in the
  registry or inferred when omitted (proxy_bitstream -> proxy_spi;
  Microsemi/Lattice -> svf); shown by fpga_info/fpga_list and exposed via
  fpga_prog_method_name() for the future program dispatch
- generalise RTCK as a neutral JTAG_RTCK, mirrored to
  PROBE_FTDI_JTAG_ENABLE_RTCK at open (FTDI-only)
- reset abstraction deferred (no clean neutral form yet); the program
  dispatch command itself lands with the SVF player

Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
2026-05-24 11:53:02 +02:00
ac883237ac jtag: cap the clock by device max_tck_khz at autoinit (phase B)
- fpga_target gains max_tck_khz (registry key), the max safe JTAG TCK
  for a part/board (0 = unspecified)
- jtag_autoinit, after identifying the chain, resolves the clock: if the
  requested JTAG_TCK_FREQ_KHZ exceeds the smallest device max, it clamps
  it and re-opens the probe once (stored probe id) to apply, then
  re-scans; within-cap / unset just report the cap
- autoinit body extracted into autoinit_run() so it can re-run after the
  re-tune; fpga_list shows maxtck

Validated on the IGLOO2/FlashPro (req 500 -> clamp 200 -> reopen -> still
detected; within-cap and unset paths don't reopen).

Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
2026-05-24 11:45:53 +02:00
70091cc4d3 fpga: add Microsemi IGLOO2 M2GL010T to the registry
IDCODE 0x0F8031CF (mask 0x0FFFFFFF, top nibble = revision) and IR
length 8 read from bsdl_files/m2gl010t-fg484.bsd. No proxy or IR
opcodes: IGLOO2 internal flash is programmed by playing a Libero SVF,
not via the Xilinx BSCAN-proxy SPI path, so those fields don't apply.

Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
2026-05-24 10:47:05 +02:00
3579c5efb0 fpga: load registry from yaml at runtime, not compile-time
- registry moves from the array in fpga.c to fpga_registry.yaml at the
  repo root, parsed via libyaml (pkg-config yaml-0.1); adding a part is
  now a YAML edit, no rebuild
- looked up CWD-relative (like bsdl_files/), overridable with
  $BS_FPGA_REGISTRY, loaded lazily once; public API unchanged
- fpga_list shows the source file (fpga_registry_source())
- add microsemi_igloo2/smartfusion2 and lattice_machxo2/3 families,
  ready for the non-Xilinx targets
- docs updated: CLAUDE.md, README, tutorial "add a target" walkthrough

Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
2026-05-24 10:19:53 +02:00