jtag: cap the clock by device max_tck_khz at autoinit (phase B)

- fpga_target gains max_tck_khz (registry key), the max safe JTAG TCK
  for a part/board (0 = unspecified)
- jtag_autoinit, after identifying the chain, resolves the clock: if the
  requested JTAG_TCK_FREQ_KHZ exceeds the smallest device max, it clamps
  it and re-opens the probe once (stored probe id) to apply, then
  re-scans; within-cap / unset just report the cap
- autoinit body extracted into autoinit_run() so it can re-run after the
  re-tune; fpga_list shows maxtck

Validated on the IGLOO2/FlashPro (req 500 -> clamp 200 -> reopen -> still
detected; within-cap and unset paths don't reopen).

Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>

fpga_registry.yaml

@@ -19,6 +19,9 @@
 #                     (omit if none is available yet)
 #   caveats           space/comma-separated flags: cclk_via_startup
 #                     (omit if none)
+#   max_tck_khz       max safe JTAG TCK in kHz for this part/board; if the
+#                     requested clock exceeds it, jtag_autoinit clamps and
+#                     re-opens at the cap (omit / 0 = unspecified)
 
 fpgas:
   # Xilinx Kintex UltraScale+ XCKU15P