jtag/fpga: prog method tag + RTCK link setting (phase C)

- fpga_target gains a prog method (proxy_spi/svf/none), set in the
  registry or inferred when omitted (proxy_bitstream -> proxy_spi;
  Microsemi/Lattice -> svf); shown by fpga_info/fpga_list and exposed via
  fpga_prog_method_name() for the future program dispatch
- generalise RTCK as a neutral JTAG_RTCK, mirrored to
  PROBE_FTDI_JTAG_ENABLE_RTCK at open (FTDI-only)
- reset abstraction deferred (no clean neutral form yet); the program
  dispatch command itself lands with the SVF player

Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>

fpga_registry.yaml

@@ -22,6 +22,9 @@
 #   max_tck_khz       max safe JTAG TCK in kHz for this part/board; if the
 #                     requested clock exceeds it, jtag_autoinit clamps and
 #                     re-opens at the cap (omit / 0 = unspecified)
+#   prog              programming backend: proxy_spi | svf | none. Omit to
+#                     infer (proxy_bitstream -> proxy_spi; Microsemi/Lattice
+#                     -> svf; else none).
 
 fpgas:
   # Xilinx Kintex UltraScale+ XCKU15P
@@ -39,6 +42,7 @@ fpgas:
     ir_jshutdown:   0x0D
     ir_isc_disable: 0x16
     caveats:        cclk_via_startup
+    prog:           proxy_spi
     # proxy_bitstream not yet built for this part (see doc/tutorial.md, Phase 2.5)
 
   # Xilinx Kintex UltraScale XCKU040 (KCU105 eval board)
@@ -57,6 +61,7 @@ fpgas:
     ir_isc_disable:  0x16
     proxy_bitstream: bscan_spi_xcku040.bit
     caveats:         cclk_via_startup
+    prog:            proxy_spi
 
   # Microsemi IGLOO2 M2GL010T (M2GL-EVAL-KIT)
   # IDCODE / IR length from bsdl_files/m2gl010t-fg484.bsd
@@ -72,3 +77,4 @@ fpgas:
     family:         microsemi_igloo2
     bsdl:           m2gl010t-fg484.bsd
     ir_length:      8
+    prog:           svf