fpga: load registry from yaml at runtime, not compile-time

- registry moves from the array in fpga.c to fpga_registry.yaml at the
  repo root, parsed via libyaml (pkg-config yaml-0.1); adding a part is
  now a YAML edit, no rebuild
- looked up CWD-relative (like bsdl_files/), overridable with
  $BS_FPGA_REGISTRY, loaded lazily once; public API unchanged
- fpga_list shows the source file (fpga_registry_source())
- add microsemi_igloo2/smartfusion2 and lattice_machxo2/3 families,
  ready for the non-Xilinx targets
- docs updated: CLAUDE.md, README, tutorial "add a target" walkthrough

Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>

fpga_registry.yaml

@@ -0,0 +1,56 @@
+# bs_explorer FPGA registry
+#
+# Loaded at runtime by modules/fpga/. Looked up relative to the current
+# directory (run bs_explorer from the repo root), or via $BS_FPGA_REGISTRY.
+#
+# One entry per programmable device. Fields:
+#   name              human-readable part name (quoted)
+#   idcode            JTAG IDCODE pattern (hex)
+#   idcode_mask       bits compared when matching (0x0FFFFFFF on Xilinx
+#                     masks the version nibble); default 0xFFFFFFFF
+#   family            xilinx_7 | xilinx_us | xilinx_usp |
+#                     microsemi_igloo2 | microsemi_smartfusion2 |
+#                     lattice_machxo2 | lattice_machxo3
+#   bsdl              basename of the .bsd in bsdl_files/
+#   ir_length         IR width in bits
+#   ir_cfg_in / ir_user1 / ir_jprogram / ir_jstart / ir_jshutdown /
+#   ir_isc_disable    private IR opcodes (hex; from the BSDL on Xilinx)
+#   proxy_bitstream   basename of the proxy .bit in bscan_proxies/
+#                     (omit if none is available yet)
+#   caveats           space/comma-separated flags: cclk_via_startup
+#                     (omit if none)
+
+fpgas:
+  # Xilinx Kintex UltraScale+ XCKU15P
+  # IDCODE / opcodes from bsdl_files/xcku15p_ffve1517.bsd, IR length 6.
+  - name:           "Xilinx Kintex UltraScale+ XCKU15P"
+    idcode:         0x04A56093
+    idcode_mask:    0x0FFFFFFF
+    family:         xilinx_usp
+    bsdl:           xcku15p_ffve1517.bsd
+    ir_length:      6
+    ir_cfg_in:      0x05
+    ir_user1:       0x02
+    ir_jprogram:    0x0B
+    ir_jstart:      0x0C
+    ir_jshutdown:   0x0D
+    ir_isc_disable: 0x16
+    caveats:        cclk_via_startup
+    # proxy_bitstream not yet built for this part (see doc/tutorial.md, Phase 2.5)
+
+  # Xilinx Kintex UltraScale XCKU040 (KCU105 eval board)
+  # IDCODE / opcodes from bsdl_files/xcku040_ffva1156.bsd, IR length 6.
+  - name:            "Xilinx Kintex UltraScale XCKU040"
+    idcode:          0x03822093
+    idcode_mask:     0x0FFFFFFF
+    family:          xilinx_us
+    bsdl:            xcku040_ffva1156.bsd
+    ir_length:       6
+    ir_cfg_in:       0x05
+    ir_user1:        0x02
+    ir_jprogram:     0x0B
+    ir_jstart:       0x0C
+    ir_jshutdown:    0x0D
+    ir_isc_disable:  0x16
+    proxy_bitstream: bscan_spi_xcku040.bit
+    caveats:         cclk_via_startup