Commit Graph

10 Commits

Author SHA1 Message Date
4329030ab9 doc: design note for extending to Lattice and Microsemi IGLOO2
Both hold config in internal flash (programmed directly over JTAG), so
the Xilinx external-flash+proxy path doesn't apply. Records two backend
strategies — native per-family (Lattice ISC / IEEE 1532) vs a generic
SVF/STAPL player (recommended for IGLOO2, whose algorithm is
proprietary) — what already generalises, and the registry/dispatch
changes needed.
2026-05-24 01:15:32 +02:00
d6b5fb572f doc: how to build a not-pre-built proxy (KU15P) in the tutorial
quartiq ships no UltraScale+ proxy, so the KU15P .bit must be built from
xilinx_bscan_spi.py (Migen + Vivado) after adding the part to the
generator's device table. Put the operational steps in the tutorial's
Phase 2.5 (where users look for a bitstream); CLAUDE.md just points to
it.
2026-05-24 01:04:44 +02:00
e987afc624 doc: mark Phase 4 done
Full flash command set (detect/read/erase/write/verify) validated on the
KCU105 via a save/erase/write-random/verify/restore round-trip.
2026-05-24 00:53:07 +02:00
71b74fa03d fpga: rename "quirk" to "caveat"
"quirk" was unclear jargon; "caveat" matches the wording already used in
the README/CLAUDE.md ("Xilinx caveats"). Renames the struct field, the
FPGA_QUIRK_* macro, the fpga_info output and the docs. No behaviour
change.
2026-05-24 00:31:47 +02:00
ca611b96fa doc: mark Phase 3 done, Phase 4 in progress
spi_flash/ landed (detect+read validated on KCU105); flash_detect and
flash_read commands done, write/erase/verify still pending.
2026-05-24 00:14:28 +02:00
8e3428788c build: Digilent backend on by default on UNIX
The driver dlopen's libdjtg/libdmgr and degrades to "no probe" if
they're absent, so building it in has no cost or dependency.
BS_ENABLE_DIGILENT now defaults ON on UNIX (needs <dlfcn.h>); disable
with -DBS_ENABLE_DIGILENT=OFF. Docs updated; also fixes the quartiq
license note in CLAUDE.md (MIT, not BSD-2).
2026-05-23 17:16:36 +02:00
952c010c63 script: shorten jtag_* command names
Drop the get_/set_/_pin/_list noise from the JTAG commands (e.g.
jtag_get_probes_list -> jtag_probes, jtag_set_spi_cs_pin -> jtag_spi_cs,
jtag_spi_rd_wr -> jtag_spi_xfer). jtag_open_probe -> jtag_open (not
jtag_probe, which would clash with jtag_probes under tab-completion).

Hard rename, no aliases. Updates the state-dump emitter, help text,
example script and docs accordingly.
2026-05-23 16:33:23 +02:00
cacbb9d00e doc: document Digilent backend and probe-open by index
CLAUDE.md/README/tutorial: optional BS_ENABLE_DIGILENT backend, why
SMT2 modules need libdjtg, and the new jtag_open_probe index. Mark
phases 2 and 2.5 done.
2026-05-23 12:07:26 +02:00
1febae7377 doc: add end-to-end tutorial
doc/tutorial.md walks from probe detection to JEDEC ID over EXTEST and
forward-references the BSCAN proxy path. Includes:
- prerequisites and build/launch
- chain scan, FPGA identification, registry lookup
- IR/DR primitive sanity check via the IDCODE register
- SPI JEDEC ID over EXTEST (with the speed caveat)
- recipe to add a new FPGA target
- troubleshooting cheat sheet

README and CLAUDE.md updated to point at it.

Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
2026-05-20 23:11:15 +02:00
bbb99ba35c add CLAUDE.md with project guide
Durable project context (architecture, roadmap, key decisions, external
references, commit conventions) so any Claude Code session on any
machine has the same baseline understanding. Machine-local facts stay
out of the repo, in ~/.claude/.

Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
2026-05-20 22:41:13 +02:00