doc: how to build a not-pre-built proxy (KU15P) in the tutorial

quartiq ships no UltraScale+ proxy, so the KU15P .bit must be built from
xilinx_bscan_spi.py (Migen + Vivado) after adding the part to the
generator's device table. Put the operational steps in the tutorial's
Phase 2.5 (where users look for a bitstream); CLAUDE.md just points to
it.

CLAUDE.md

@@ -124,8 +124,9 @@ then `JSTART` and check `DONE`.
 ## External references
 
 - **BSCAN proxy bitstreams**: `quartiq/bscan_spi_bitstreams` (MIT).
-  Pre-built `.bit` for most Xilinx parts; Migen sources to rebuild any
-  part that's missing (needs Vivado).
+  Pre-built `.bit` for many Xilinx parts; Migen sources to rebuild any
+  part that's missing (needs Vivado). Building a proxy that isn't
+  pre-built (e.g. the KU15P) is covered in `doc/tutorial.md`, Phase 2.5.
 - **Reference host-side implementation**: `openocd/src/flash/nor/jtagspi.c`.
   Defines the proxy protocol (header with bit count + CS state, then
   payload). Don't reinvent — match what OpenOCD does so we share the