fpga: rename "quirk" to "caveat"
"quirk" was unclear jargon; "caveat" matches the wording already used in
the README/CLAUDE.md ("Xilinx caveats"). Renames the struct field, the
FPGA_QUIRK_* macro, the fpga_info output and the docs. No behaviour
change.
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@@ -49,7 +49,7 @@ Adding a feature usually means adding a new script command in
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| Phase | Module | Status | Summary |
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|-------|--------|--------|---------|
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| 1 | `bs/` cleanup, REPL polish, README | **done** (commit `7cb3627`) | Fix format-strings, delete dead code, tab-completion, banner |
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| 2 | `fpga/` | **done** (commit `545fe09`) | Per-target descriptor (IDCODE, BSDL, IR codes, proxy path, quirks). Compile-time registry. |
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| 2 | `fpga/` | **done** (commit `545fe09`) | Per-target descriptor (IDCODE, BSDL, IR codes, proxy path, caveats). Compile-time registry. |
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| 2.5 | `bscan_spi/` | **done** (commit `dec0d14`) | Load BSCAN proxy bitstream via `CFG_IN`, expose fast `bscan_spi_xfer()` via `USER1`. Required for realistic flashing speeds. |
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| 3 | `spi_flash/` | **done** (commit `c4afe87`) | Chip DB (JEDEC ID → page/sector/cmd set) + generic `read/erase/program/verify` over an `xfer` callback. detect+read validated on KCU105; erase/program implemented but not yet hardware-tested. |
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| 4 | script commands | in progress | `flash_detect` + `flash_read` done (read-only, validated). `flash_write/erase/verify` pending — destructive on a config flash, test carefully. |
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@@ -87,7 +87,7 @@ derived from the BSDL alone:
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- `cfg_in_ir_code`, `user1_ir_code`, `jprogram_ir_code` — Xilinx-specific
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private IR opcodes (read from BSDL when available)
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- `proxy_bitstream_path` — path to the BSCAN proxy `.bit` for this part
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- `quirks` — flags for known caveats (e.g. CCLK via STARTUPE3)
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- `caveats` — flags for known hardware gotchas (e.g. CCLK via STARTUPE3)
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Registry is a compile-time array. Adding a part = one entry + its
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`.bsd` in `bsdl_files/` + its proxy `.bit` in `bscan_proxies/`.
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