François
c3bb00cb4d
Major additions, all wired end-to-end with doctest coverage:
- Altium netlist importer (`imports/import_altium.{hpp,cpp}`): two-pass
parser for `[ ]` parts and `( )` signals; `System::Load` no longer has
the IMPORT_ALTIUM hole.
- `duplicate <src> <dst>` deep-copies a module (signals, parts, pins,
rewired signals); connections excluded by design.
- Nets (`system/nets.{hpp,cpp}`): BFS over `Connection::pin_map` to
return the transitive (Module, Signal) closure. `verify` extended with
a second pass flagging Power↔GndShield inconsistencies in bridged
nets; new `net <module> <signal>` command for inspection.
- Canonical pin names (`system/pin_name.{hpp,cpp}`): zero-padded digit
suffix lets A1 ↔ A001 pair via `IdentityTransform` and
`CheckIdentityCompatible` without losing the imported notation.
- Component classification (`system/component_kind.{hpp,cpp}`):
`Part::kind` inferred at construction from the reference-designator
prefix (longest-match: LED/TP/SW/FB/MK/MP/MH/HS/RA/RN/RP/RV first,
then R/C/L/F/D/Q/U/J/P/Y/X/S).
- Identity wiring tolerance: `CheckIdentityCompatible` accepts the
subset case (typical when one importer drops NC pins, e.g. Altium)
and surfaces orphans as an info string. `FillIdentityNCs`
materialises orphan canonical positions as NC pins on the missing
side at connect time.
- Connector layout preparation: `pin_layout(kind)` and
`FillPartFromLayout(part, kind)` stubs in `pin_role`, called from
`set-type`. Empty today; populate alongside `vpx_3u_role`.
- TUI scrollback: PageUp/PageDown step 10 lines, Home/End jump to
ends; `Print()` snaps back to the tail.
- `set <name> <value>` declares session variables; `$name` / `${name}`
expanded inside `Finalize` between canonical-form recording and the
action call — history and script-save preserve `$var` references.
- Long `source` scripts now show a centred "Computing…" modal with a
N/M progress counter. Driven by a ticker thread that posts one
paced `Event::Special` per processed line, ack'd by the main thread,
so heavy lines don't backlog ticks and freeze the counter.
Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
87 lines
2.6 KiB
Plaintext
87 lines
2.6 KiB
Plaintext
# essim system bring-up script.
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new
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# ---------------------------------------------------------------- variables
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set test_dir /home/francois/Projets/essim_test
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set bpb_nets $test_dir/BPB-2177-10222_NETLIST_3_1.qcv
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set bkp_nets $test_dir/MERCVPX3UBPA_20221122.NET
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set cb3p_nets $test_dir/CB3P-6359-10232_NETLIST_3_0.qcv
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set vdn_nets $test_dir/VDN-2910.qcv
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set cob_nets $test_dir/COB-2277_NETLIST_10211_2_0.qcv
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set ssu_nets $test_dir/SSU-2134_PCB873.qcv
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# ---------------------------------------------------------------- modules
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load vdn1 $vdn_nets mentor
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duplicate vdn1 vdn2
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duplicate vdn1 vdn3
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load bpb $bpb_nets mentor
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load bkp $bkp_nets altium
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load cb3p $cb3p_nets mentor
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load cob $cob_nets mentor
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load ssu $ssu_nets mentor
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# ---------------------------------------------------------------- VPX tags
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# Backplane payload-side connectors on BKP, one slot per (Jx0,Jx1,Jx2):
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# J2x → VDN1, J3x → VDN2, J4x → VDN3, J5x → CB3P.
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set-type bkp J20 vpx-3u-bkp-p0
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set-type bkp J21 vpx-3u-bkp-p1
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set-type bkp J22 vpx-3u-bkp-p2
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set-type bkp J30 vpx-3u-bkp-p0
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set-type bkp J31 vpx-3u-bkp-p1
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set-type bkp J32 vpx-3u-bkp-p2
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set-type bkp J40 vpx-3u-bkp-p0
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set-type bkp J41 vpx-3u-bkp-p1
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set-type bkp J42 vpx-3u-bkp-p2
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set-type bkp J50 vpx-3u-bkp-p0
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set-type bkp J51 vpx-3u-bkp-p1
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set-type bkp J52 vpx-3u-bkp-p2
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# Payload connectors on each plug-in card.
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set-type vdn1 P0 vpx-3u-payload-p0
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set-type vdn1 P1 vpx-3u-payload-p1
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set-type vdn1 P2 vpx-3u-payload-p2
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set-type vdn2 P0 vpx-3u-payload-p0
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set-type vdn2 P1 vpx-3u-payload-p1
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set-type vdn2 P2 vpx-3u-payload-p2
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set-type vdn3 P0 vpx-3u-payload-p0
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set-type vdn3 P1 vpx-3u-payload-p1
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set-type vdn3 P2 vpx-3u-payload-p2
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set-type cb3p P0 vpx-3u-payload-p0
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set-type cb3p P1 vpx-3u-payload-p1
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set-type cb3p P2 vpx-3u-payload-p2
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# ---------------------------------------------------------------- VPX wiring
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# Each connect dispatches via the registered vpx-3u transform.
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connect bkp J20 vdn1 P0
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connect bkp J21 vdn1 P1
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connect bkp J22 vdn1 P2
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connect bkp J30 vdn2 P0
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connect bkp J31 vdn2 P1
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connect bkp J32 vdn2 P2
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connect bkp J40 vdn3 P0
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connect bkp J41 vdn3 P1
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connect bkp J42 vdn3 P2
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connect bkp J50 cb3p P0
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connect bkp J51 cb3p P1
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connect bkp J52 cb3p P2
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# ---------------------------------------------------------------- non-VPX
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# Both ends untagged → IdentityTransform (matches by canonical pin name,
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# so e.g. A1 ↔ A001 is paired thanks to canonical_pin_name).
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connect cob P3 ssu P6
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connect bkp J1 ssu P1
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# BPB ↔ BKP
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connect bkp P100 bpb J100
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connect bkp P101 bpb J101
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connect bkp P102 bpb J102
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# BPB ↔ COB
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connect bpb J0 cob P0
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connect bpb J1 cob P1
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connect bpb J2 cob P2
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