François
9ad776268e
Restructure in anticipation of programming ARM CPUs (ARM7/9 via EmbeddedICE, e.g. over an Olimex ARM-USB-OCD); FPGA path unchanged. - modules/fpga -> modules/target; fpga_target -> jtag_target with a `kind` (fpga|cpu) and grouped fpga/cpu sub-structs; data/targets.yaml (env BS_TARGETS); API target_*; commands target_list/target_info (kind-aware). Add arm7/arm9 families, arm_flash prog, embeddedice debug, and cpu fields (ram_base/size, flash_base/size). - new program/: `program <dev> <file>` dispatches by the target's prog (svf wired; proxy_spi points at the flash workflow; arm_flash -> arm_debug). - new arm_debug/: EmbeddedICE halt/resume/mem + arm_flash backend declared, not implemented yet. - bscan_* take const jtag_target* and read the fpga sub-struct. - data/probes.yaml: arm-usb-ocd profile slot; data/targets.yaml: an ARM7 example entry. Docs + an ARM-debug design note in CLAUDE.md. Builds; FPGA path re-validated on the IGLOO2 (target_list shows the CPU example; jtag_open/autoinit/program 0 <svf> all work). Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
103 lines
4.1 KiB
YAML
103 lines
4.1 KiB
YAML
# bs_explorer JTAG target registry (FPGAs and CPUs)
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#
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# Loaded at runtime by src/modules/target/. Looked up relative to the
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# current directory (run bs_explorer from the repo root), or via
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# $BS_TARGETS.
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#
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# One flat entry per device under `targets:`. `kind` selects which
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# fields apply. Common fields:
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# name human-readable part name (quoted)
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# idcode JTAG IDCODE pattern (hex)
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# idcode_mask bits compared when matching (0x0FFFFFFF masks a
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# version nibble); default 0xFFFFFFFF
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# kind fpga | cpu (default fpga)
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# family xilinx_7/us/usp | microsemi_igloo2/smartfusion2 |
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# lattice_machxo2/3 | arm7 | arm9
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# ir_length IR width in bits
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# prog backend: proxy_spi | svf | arm_flash | none.
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# Omit to infer (proxy -> proxy_spi; Microsemi/Lattice
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# -> svf; cpu with a debug iface -> arm_flash).
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# max_tck_khz max safe JTAG TCK in kHz; jtag_autoinit clamps and
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# re-opens if exceeded (omit / 0 = unspecified)
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#
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# FPGA fields (kind: fpga):
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# bsdl basename of the .bsd in data/bsdl_files/
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# ir_cfg_in / ir_user1 / ir_jprogram / ir_jstart / ir_jshutdown /
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# ir_isc_disable private IR opcodes (hex; from the BSDL on Xilinx)
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# proxy_bitstream basename of the proxy .bit in data/bscan_proxies/
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# caveats space/comma-separated flags: cclk_via_startup
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#
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# CPU fields (kind: cpu):
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# debug debug transport: embeddedice (ARM7/ARM9)
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# ram_base/ram_size on-chip work-RAM for the flash loader (hex)
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# flash_base/flash_size on-chip flash region (hex)
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targets:
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# Xilinx Kintex UltraScale+ XCKU15P
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# IDCODE / opcodes from data/bsdl_files/xcku15p_ffve1517.bsd, IR length 6.
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- name: "Xilinx Kintex UltraScale+ XCKU15P"
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kind: fpga
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idcode: 0x04A56093
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idcode_mask: 0x0FFFFFFF
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family: xilinx_usp
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bsdl: xcku15p_ffve1517.bsd
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ir_length: 6
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ir_cfg_in: 0x05
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ir_user1: 0x02
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ir_jprogram: 0x0B
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ir_jstart: 0x0C
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ir_jshutdown: 0x0D
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ir_isc_disable: 0x16
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caveats: cclk_via_startup
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prog: proxy_spi
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# proxy_bitstream not yet built for this part (see doc/tutorial.md, Phase 2.5)
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# Xilinx Kintex UltraScale XCKU040 (KCU105 eval board)
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- name: "Xilinx Kintex UltraScale XCKU040"
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kind: fpga
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idcode: 0x03822093
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idcode_mask: 0x0FFFFFFF
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family: xilinx_us
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bsdl: xcku040_ffva1156.bsd
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ir_length: 6
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ir_cfg_in: 0x05
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ir_user1: 0x02
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ir_jprogram: 0x0B
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ir_jstart: 0x0C
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ir_jshutdown: 0x0D
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ir_isc_disable: 0x16
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proxy_bitstream: bscan_spi_xcku040.bit
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caveats: cclk_via_startup
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prog: proxy_spi
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# Microsemi IGLOO2 M2GL010T (M2GL-EVAL-KIT)
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# IDCODE / IR length from data/bsdl_files/m2gl010t-fg484.bsd
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# IDCODE_REGISTER "XXXX1111100000000011000111001111" -> 0x0F8031CF
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# (top nibble = silicon revision, masked off). Programmed by playing
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# an SVF exported from Libero, not the Xilinx proxy path.
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- name: "Microsemi IGLOO2 M2GL010T"
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kind: fpga
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idcode: 0x0F8031CF
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idcode_mask: 0x0FFFFFFF
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family: microsemi_igloo2
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bsdl: m2gl010t-fg484.bsd
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ir_length: 8
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prog: svf
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# --- CPU example (ARM7TDMI-S, LPC2148-class) ----------------------
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# EXAMPLE entry: verify the IDCODE, IR length and RAM/flash regions
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# against your actual part before relying on it. The arm_flash backend
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# is not implemented yet (see src/modules/arm_debug/ and CLAUDE.md).
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- name: "ARM7TDMI-S (example, e.g. NXP LPC2148)"
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kind: cpu
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idcode: 0x4F1F0F0F
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idcode_mask: 0x0FFFFFFF
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family: arm7
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ir_length: 4
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debug: embeddedice
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ram_base: 0x40000000
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ram_size: 0x8000
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flash_base: 0x0
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flash_size: 0x7D000
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prog: arm_flash
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