François
71b74fa03d
"quirk" was unclear jargon; "caveat" matches the wording already used in
the README/CLAUDE.md ("Xilinx caveats"). Renames the struct field, the
FPGA_QUIRK_* macro, the fpga_info output and the docs. No behaviour
change.
85 lines
2.7 KiB
C
85 lines
2.7 KiB
C
#include <stddef.h>
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#include "fpga.h"
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static const fpga_target fpga_registry[] = {
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/* Xilinx Kintex UltraScale+ XCKU15P
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* IDCODE_REGISTER and INSTRUCTION_OPCODE values come from
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* bsdl_files/xcku15p_ffve1517.bsd
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* IR length 6 bits, version nibble (bits 31:28) ignored. */
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{
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.name = "Xilinx Kintex UltraScale+ XCKU15P",
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.idcode = 0x04A56093,
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.idcode_mask = 0x0FFFFFFF,
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.family = FPGA_FAMILY_XILINX_USP,
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.bsdl_filename = "xcku15p_ffve1517.bsd",
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.ir_length = 6,
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.ir_cfg_in = 0x05,
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.ir_user1 = 0x02,
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.ir_jprogram = 0x0B,
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.ir_jstart = 0x0C,
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.ir_jshutdown = 0x0D,
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.ir_isc_disable = 0x16,
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.proxy_bitstream = NULL, /* TODO Phase 2.5: bscan_spi_xcku15p.bit */
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.caveats = FPGA_CAVEAT_CCLK_VIA_STARTUP,
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},
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/* Xilinx Kintex UltraScale XCKU040 (KCU105 eval board)
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* IDCODE_REGISTER and INSTRUCTION_OPCODE values come from
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* bsdl_files/xcku040_ffva1156.bsd
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* IR length 6 bits, version nibble (bits 31:28) ignored. */
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{
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.name = "Xilinx Kintex UltraScale XCKU040",
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.idcode = 0x03822093,
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.idcode_mask = 0x0FFFFFFF,
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.family = FPGA_FAMILY_XILINX_US,
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.bsdl_filename = "xcku040_ffva1156.bsd",
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.ir_length = 6,
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.ir_cfg_in = 0x05,
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.ir_user1 = 0x02,
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.ir_jprogram = 0x0B,
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.ir_jstart = 0x0C,
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.ir_jshutdown = 0x0D,
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.ir_isc_disable = 0x16,
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.proxy_bitstream = "bscan_spi_xcku040.bit",
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.caveats = FPGA_CAVEAT_CCLK_VIA_STARTUP,
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},
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};
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#define FPGA_REGISTRY_LEN ((int)(sizeof(fpga_registry) / sizeof(fpga_registry[0])))
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int fpga_get_target_count(void)
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{
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return FPGA_REGISTRY_LEN;
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}
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const fpga_target *fpga_get_target_by_index(int index)
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{
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if (index < 0 || index >= FPGA_REGISTRY_LEN) {
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return NULL;
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}
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return &fpga_registry[index];
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}
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const fpga_target *fpga_lookup_by_idcode(unsigned long idcode)
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{
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int i;
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for (i = 0; i < FPGA_REGISTRY_LEN; i++) {
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const fpga_target *t = &fpga_registry[i];
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if ((idcode & t->idcode_mask) == (t->idcode & t->idcode_mask)) {
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return t;
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}
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}
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return NULL;
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}
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const char *fpga_family_name(fpga_family f)
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{
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switch (f) {
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case FPGA_FAMILY_XILINX_7: return "Xilinx 7-Series";
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case FPGA_FAMILY_XILINX_US: return "Xilinx UltraScale";
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case FPGA_FAMILY_XILINX_USP: return "Xilinx UltraScale+";
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case FPGA_FAMILY_UNKNOWN:
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default: return "Unknown";
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}
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}
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