#include <stddef.h>

#include "fpga.h"

static const fpga_target fpga_registry[] = {
    /* Xilinx Kintex UltraScale+ XCKU15P
     * IDCODE_REGISTER and INSTRUCTION_OPCODE values come from
     *   bsdl_files/xcku15p_ffve1517.bsd
     * IR length 6 bits, version nibble (bits 31:28) ignored. */
    {
        .name             = "Xilinx Kintex UltraScale+ XCKU15P",
        .idcode           = 0x04A56093,
        .idcode_mask      = 0x0FFFFFFF,
        .family           = FPGA_FAMILY_XILINX_USP,
        .bsdl_filename    = "xcku15p_ffve1517.bsd",
        .ir_length        = 6,
        .ir_cfg_in        = 0x05,
        .ir_user1         = 0x02,
        .ir_jprogram      = 0x0B,
        .ir_jstart        = 0x0C,
        .ir_jshutdown     = 0x0D,
        .ir_isc_disable   = 0x16,
        .proxy_bitstream  = NULL,   /* TODO Phase 2.5: bscan_spi_xcku15p.bit */
        .caveats          = FPGA_CAVEAT_CCLK_VIA_STARTUP,
    },
    /* Xilinx Kintex UltraScale XCKU040 (KCU105 eval board)
     * IDCODE_REGISTER and INSTRUCTION_OPCODE values come from
     *   bsdl_files/xcku040_ffva1156.bsd
     * IR length 6 bits, version nibble (bits 31:28) ignored. */
    {
        .name             = "Xilinx Kintex UltraScale XCKU040",
        .idcode           = 0x03822093,
        .idcode_mask      = 0x0FFFFFFF,
        .family           = FPGA_FAMILY_XILINX_US,
        .bsdl_filename    = "xcku040_ffva1156.bsd",
        .ir_length        = 6,
        .ir_cfg_in        = 0x05,
        .ir_user1         = 0x02,
        .ir_jprogram      = 0x0B,
        .ir_jstart        = 0x0C,
        .ir_jshutdown     = 0x0D,
        .ir_isc_disable   = 0x16,
        .proxy_bitstream  = "bscan_spi_xcku040.bit",
        .caveats          = FPGA_CAVEAT_CCLK_VIA_STARTUP,
    },
};

#define FPGA_REGISTRY_LEN ((int)(sizeof(fpga_registry) / sizeof(fpga_registry[0])))

int fpga_get_target_count(void)
{
    return FPGA_REGISTRY_LEN;
}

const fpga_target *fpga_get_target_by_index(int index)
{
    if (index < 0 || index >= FPGA_REGISTRY_LEN) {
        return NULL;
    }
    return &fpga_registry[index];
}

const fpga_target *fpga_lookup_by_idcode(unsigned long idcode)
{
    int i;
    for (i = 0; i < FPGA_REGISTRY_LEN; i++) {
        const fpga_target *t = &fpga_registry[i];
        if ((idcode & t->idcode_mask) == (t->idcode & t->idcode_mask)) {
            return t;
        }
    }
    return NULL;
}

const char *fpga_family_name(fpga_family f)
{
    switch (f) {
    case FPGA_FAMILY_XILINX_7:   return "Xilinx 7-Series";
    case FPGA_FAMILY_XILINX_US:  return "Xilinx UltraScale";
    case FPGA_FAMILY_XILINX_USP: return "Xilinx UltraScale+";
    case FPGA_FAMILY_UNKNOWN:
    default:                     return "Unknown";
    }
}