francois
dec0d14a06
Low-level JTAG primitives operating directly on jc->io_functions (single-device chain assumed), independent of jtag_core: - bscan_set_ir - bscan_shift_dr (TDI/TDO, LSB-first packing) - bscan_idle_cycles High-level operations driven by an fpga_target descriptor: - bscan_load_bitstream: JPROGRAM -> CFG_IN -> shift (bit-reversed for Xilinx) -> JSTART -> idle -> BYPASS - bscan_load_bitstream_file: parses the Xilinx .bit container header (sections a/b/c/d/e), falls back to raw .bin bscan_spi_xfer is stubbed: the quartiq jtagspi protocol details will be wired once we have a proxy .bit to validate against (OpenOCD src/flash/nor/jtagspi.c is the host-side reference). Three new script commands: - bscan_set_ir <opcode_hex> <ir_length> - bscan_shift_dr <nbits> (writes zeros, prints captured TDO) - bscan_load_bitstream <device> <path> The sanity check for a healthy primitive on KU15P: jtag_init_scan; bscan_set_ir 9 6; bscan_shift_dr 32 -> 04 A5 60 93 Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
60 lines
2.3 KiB
C
60 lines
2.3 KiB
C
#ifndef _BSCAN_SPI_H
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#define _BSCAN_SPI_H
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/*
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* BSCAN-proxy SPI bridge (Phase 2.5).
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*
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* Provides:
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* - low-level JTAG primitives (set_ir, shift_dr, idle_cycles) that
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* operate directly on jc->io_functions, leaving jtag_core untouched;
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* - bitstream loading via CFG_IN to install a BSCAN proxy in the FPGA
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* fabric;
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* - a fast SPI transfer routine via USER1 once the proxy is loaded.
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*
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* Current assumption: single device on the JTAG chain. Multi-device
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* support requires knowing the IR length of bypassed devices; defer.
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*
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* The SPI transfer entry point is wired against the quartiq jtagspi
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* proxy convention but the protocol header still needs to be confirmed
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* against an actual proxy bitstream (see openocd src/flash/nor/jtagspi.c).
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*/
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#include <stddef.h>
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#include <stdint.h>
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#include "jtag_core/jtag_core.h"
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#include "fpga/fpga.h"
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/* --- Low-level primitives (single-device chain) -------------------- */
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/* Shift `opcode` into IR. `ir_length` is the IR width in bits. */
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int bscan_set_ir(jtag_core *jc, unsigned int opcode, int ir_length);
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/* Shift `nbits` through DR. `tdi` may be NULL (shifts zeros).
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* `tdo` may be NULL (write only). Both buffers are LSB-first per byte. */
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int bscan_shift_dr(jtag_core *jc, const uint8_t *tdi, uint8_t *tdo, int nbits);
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/* Emit `ncycles` TCK cycles while staying in Run-Test/Idle. */
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int bscan_idle_cycles(jtag_core *jc, int ncycles);
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/* --- High-level operations ---------------------------------------- */
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/* Load a raw bitstream payload (no .bit container header) into the
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* FPGA via JPROGRAM -> CFG_IN -> shift -> JSTART. Bit-reverses each
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* byte before shifting (Xilinx convention). */
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int bscan_load_bitstream(jtag_core *jc, const fpga_target *t,
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const uint8_t *data, size_t nbytes);
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/* Convenience wrapper: read a file and load it. Detects the Xilinx
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* .bit header and skips it; otherwise treats the file as raw payload. */
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int bscan_load_bitstream_file(jtag_core *jc, const fpga_target *t,
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const char *path);
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/* Transfer `nbytes` of SPI data through the BSCAN proxy (USER1 DR).
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* Placeholder: protocol details deferred until an actual proxy
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* bitstream is available for testing. */
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int bscan_spi_xfer(jtag_core *jc, const fpga_target *t,
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const uint8_t *tx, uint8_t *rx, size_t nbytes);
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#endif
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