phase 2.5: add bscan_spi/ — BSCAN proxy infrastructure
Low-level JTAG primitives operating directly on jc->io_functions (single-device chain assumed), independent of jtag_core: - bscan_set_ir - bscan_shift_dr (TDI/TDO, LSB-first packing) - bscan_idle_cycles High-level operations driven by an fpga_target descriptor: - bscan_load_bitstream: JPROGRAM -> CFG_IN -> shift (bit-reversed for Xilinx) -> JSTART -> idle -> BYPASS - bscan_load_bitstream_file: parses the Xilinx .bit container header (sections a/b/c/d/e), falls back to raw .bin bscan_spi_xfer is stubbed: the quartiq jtagspi protocol details will be wired once we have a proxy .bit to validate against (OpenOCD src/flash/nor/jtagspi.c is the host-side reference). Three new script commands: - bscan_set_ir <opcode_hex> <ir_length> - bscan_shift_dr <nbits> (writes zeros, prints captured TDO) - bscan_load_bitstream <device> <path> The sanity check for a healthy primitive on KU15P: jtag_init_scan; bscan_set_ir 9 6; bscan_shift_dr 32 -> 04 A5 60 93 Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
This commit is contained in:
7
modules/bscan_spi/CMakeLists.txt
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7
modules/bscan_spi/CMakeLists.txt
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@@ -0,0 +1,7 @@
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set(SOURCE_DIR "${CMAKE_CURRENT_SOURCE_DIR}")
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file(GLOB_RECURSE ALL_SOURCES "*.c")
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include_directories(${CMAKE_CURRENT_SOURCE_DIR}/..)
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add_library(bscan_spi ${ALL_SOURCES})
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277
modules/bscan_spi/bscan_spi.c
Normal file
277
modules/bscan_spi/bscan_spi.c
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@@ -0,0 +1,277 @@
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include "bscan_spi.h"
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/* JTAG byte format expected by drv_TXRX_DATA / drv_TX_TMS:
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* bit 0 (JTAG_STR_DOUT) = TDI value
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* bit 1 (JTAG_STR_TMS) = TMS value
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* bit 4 (JTAG_STR_DIN) = TDO returned by the driver (1 if TDO was high).
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* In practice, jtag_core treats the input byte as "non-zero if TDO=1",
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* so we just check buf_in[i] != 0 on read. */
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static int drv_ok(jtag_core *jc)
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{
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return jc && jc->io_functions.drv_TX_TMS && jc->io_functions.drv_TXRX_DATA;
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}
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/* --- Low-level primitives ----------------------------------------- */
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int bscan_set_ir(jtag_core *jc, unsigned int opcode, int ir_length)
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{
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unsigned char tms_buf[8];
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unsigned char *data_buf;
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int i;
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if (!drv_ok(jc) || ir_length <= 0 || ir_length > 32) {
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return -1;
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}
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/* Idle -> Select-DR -> Select-IR -> Capture-IR -> Shift-IR */
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tms_buf[0] = JTAG_STR_TMS;
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tms_buf[1] = JTAG_STR_TMS;
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tms_buf[2] = 0;
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tms_buf[3] = 0;
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jc->io_functions.drv_TX_TMS(jc, tms_buf, 4);
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/* Shift IR LSB first; raise TMS on the last bit (-> Exit1-IR) */
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data_buf = malloc(ir_length);
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if (!data_buf) return -1;
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for (i = 0; i < ir_length; i++) {
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data_buf[i] = ((opcode >> i) & 1u) ? JTAG_STR_DOUT : 0;
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if (i == ir_length - 1) {
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data_buf[i] |= JTAG_STR_TMS;
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}
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}
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jc->io_functions.drv_TXRX_DATA(jc, data_buf, NULL, ir_length);
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free(data_buf);
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/* Exit1-IR -> Update-IR -> Idle */
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tms_buf[0] = JTAG_STR_TMS;
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tms_buf[1] = 0;
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jc->io_functions.drv_TX_TMS(jc, tms_buf, 2);
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return 0;
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}
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int bscan_shift_dr(jtag_core *jc, const uint8_t *tdi, uint8_t *tdo, int nbits)
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{
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unsigned char tms_buf[8];
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unsigned char *buf_out, *buf_in;
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int i;
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if (!drv_ok(jc) || nbits <= 0) {
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return -1;
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}
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/* Idle -> Select-DR -> Capture-DR -> Shift-DR */
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tms_buf[0] = JTAG_STR_TMS;
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tms_buf[1] = 0;
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tms_buf[2] = 0;
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jc->io_functions.drv_TX_TMS(jc, tms_buf, 3);
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buf_out = malloc(nbits);
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if (!buf_out) return -1;
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buf_in = tdo ? malloc(nbits) : NULL;
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if (tdo && !buf_in) { free(buf_out); return -1; }
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for (i = 0; i < nbits; i++) {
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uint8_t bit = 0;
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if (tdi) {
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bit = (tdi[i / 8] >> (i & 7)) & 1u;
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}
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buf_out[i] = bit ? JTAG_STR_DOUT : 0;
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if (i == nbits - 1) {
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buf_out[i] |= JTAG_STR_TMS;
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}
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}
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jc->io_functions.drv_TXRX_DATA(jc, buf_out, buf_in, nbits);
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if (tdo && buf_in) {
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memset(tdo, 0, (size_t)((nbits + 7) / 8));
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for (i = 0; i < nbits; i++) {
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if (buf_in[i]) {
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tdo[i / 8] |= (uint8_t)(1u << (i & 7));
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}
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}
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}
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free(buf_out);
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free(buf_in);
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/* Exit1-DR -> Update-DR -> Idle */
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tms_buf[0] = JTAG_STR_TMS;
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tms_buf[1] = 0;
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jc->io_functions.drv_TX_TMS(jc, tms_buf, 2);
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return 0;
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}
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int bscan_idle_cycles(jtag_core *jc, int ncycles)
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{
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unsigned char *buf;
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int i;
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if (!drv_ok(jc) || ncycles <= 0) {
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return -1;
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}
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buf = malloc(ncycles);
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if (!buf) return -1;
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for (i = 0; i < ncycles; i++) buf[i] = 0;
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jc->io_functions.drv_TX_TMS(jc, buf, ncycles);
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free(buf);
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return 0;
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}
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/* --- High-level operations ---------------------------------------- */
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static uint8_t reverse_bits(uint8_t b)
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{
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b = (uint8_t)(((b & 0xF0u) >> 4) | ((b & 0x0Fu) << 4));
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b = (uint8_t)(((b & 0xCCu) >> 2) | ((b & 0x33u) << 2));
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b = (uint8_t)(((b & 0xAAu) >> 1) | ((b & 0x55u) << 1));
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return b;
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}
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int bscan_load_bitstream(jtag_core *jc, const fpga_target *t,
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const uint8_t *data, size_t nbytes)
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{
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uint8_t *reversed;
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unsigned int bypass;
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size_t i;
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if (!drv_ok(jc) || !t || !data || nbytes == 0) return -1;
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if (!t->ir_jprogram || !t->ir_cfg_in || !t->ir_jstart) {
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/* No configuration opcodes known for this family. */
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return -1;
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}
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/* JPROGRAM clears the configuration memory. Min ~10k TCK cycles
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* to wait for INIT_B to go high before CFG_IN.
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* TODO: poll INIT_B via SAMPLE instead of fixed wait. */
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if (bscan_set_ir(jc, t->ir_jprogram, t->ir_length) < 0) return -1;
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bscan_idle_cycles(jc, 10000);
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/* CFG_IN routes DR shifts to the configuration interface. */
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if (bscan_set_ir(jc, t->ir_cfg_in, t->ir_length) < 0) return -1;
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/* Xilinx bitstream bytes must be bit-reversed before JTAG shift
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* (configuration interface latches MSB first, JTAG shifts LSB first). */
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reversed = malloc(nbytes);
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if (!reversed) return -1;
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for (i = 0; i < nbytes; i++) {
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reversed[i] = reverse_bits(data[i]);
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}
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if (bscan_shift_dr(jc, reversed, NULL, (int)(nbytes * 8)) < 0) {
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free(reversed);
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return -1;
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}
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free(reversed);
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/* JSTART triggers the fabric startup. UG470/UG570: ≥12 cycles in
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* Idle to complete the sequence. Use 2000 for margin. */
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if (bscan_set_ir(jc, t->ir_jstart, t->ir_length) < 0) return -1;
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bscan_idle_cycles(jc, 2000);
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/* Park on BYPASS (all 1s) so other operations don't trip on a
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* lingering instruction. */
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bypass = (t->ir_length >= 32) ? 0xFFFFFFFFu : ((1u << t->ir_length) - 1u);
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bscan_set_ir(jc, bypass, t->ir_length);
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return 0;
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}
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/* Parse a Xilinx .bit container; return offset and length of the raw
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* bitstream payload. Returns -1 if not a .bit. */
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static int xilinx_bit_payload(const uint8_t *buf, size_t buflen,
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size_t *out_off, size_t *out_len)
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{
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size_t off = 0;
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uint16_t hdr_len;
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if (buflen < 13) return -1;
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/* First 2 bytes are big-endian length of a magic block (typically 0x0009),
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* followed by 9 magic bytes. */
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hdr_len = (uint16_t)((buf[0] << 8) | buf[1]);
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if (hdr_len != 0x0009) return -1;
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off = 2 + hdr_len;
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/* Then 2 bytes (0x0001) and ASCII-tagged sections a/b/c/d, then 'e'
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* followed by 4 bytes big-endian length of the bitstream payload. */
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if (off + 2 > buflen) return -1;
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off += 2;
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while (off < buflen) {
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uint8_t tag = buf[off++];
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if (tag == 'e') {
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uint32_t bit_len;
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if (off + 4 > buflen) return -1;
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bit_len = ((uint32_t)buf[off] << 24) | ((uint32_t)buf[off + 1] << 16)
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| ((uint32_t)buf[off + 2] << 8) | (uint32_t)buf[off + 3];
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off += 4;
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if (off + bit_len > buflen) return -1;
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*out_off = off;
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*out_len = bit_len;
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return 0;
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}
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if (tag >= 'a' && tag <= 'd') {
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if (off + 2 > buflen) return -1;
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hdr_len = (uint16_t)((buf[off] << 8) | buf[off + 1]);
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off += 2 + hdr_len;
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} else {
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return -1;
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}
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}
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return -1;
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}
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int bscan_load_bitstream_file(jtag_core *jc, const fpga_target *t,
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const char *path)
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{
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FILE *f;
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long size;
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uint8_t *buf;
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size_t payload_off = 0;
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size_t payload_len = 0;
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int ret;
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if (!path) return -1;
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f = fopen(path, "rb");
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if (!f) return -1;
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if (fseek(f, 0, SEEK_END) != 0) { fclose(f); return -1; }
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size = ftell(f);
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if (size <= 0) { fclose(f); return -1; }
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rewind(f);
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buf = malloc((size_t)size);
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if (!buf) { fclose(f); return -1; }
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if (fread(buf, 1, (size_t)size, f) != (size_t)size) {
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free(buf); fclose(f); return -1;
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}
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fclose(f);
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if (xilinx_bit_payload(buf, (size_t)size, &payload_off, &payload_len) < 0) {
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/* Treat as raw .bin */
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payload_off = 0;
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payload_len = (size_t)size;
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}
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ret = bscan_load_bitstream(jc, t, buf + payload_off, payload_len);
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free(buf);
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return ret;
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}
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int bscan_spi_xfer(jtag_core *jc, const fpga_target *t,
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const uint8_t *tx, uint8_t *rx, size_t nbytes)
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{
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/* Skeleton — to be completed once we can validate the protocol
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* against an actual quartiq jtagspi proxy bitstream.
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*
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* Expected outline:
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* - bscan_set_ir(jc, t->ir_user1, t->ir_length)
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* - bscan_shift_dr with <header><payload>, where the header
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* encodes the bit count and CS state per the proxy convention.
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* - extract MISO bytes from the TDO data. */
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(void)jc; (void)t; (void)tx; (void)rx; (void)nbytes;
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return -1;
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}
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59
modules/bscan_spi/bscan_spi.h
Normal file
59
modules/bscan_spi/bscan_spi.h
Normal file
@@ -0,0 +1,59 @@
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#ifndef _BSCAN_SPI_H
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#define _BSCAN_SPI_H
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/*
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* BSCAN-proxy SPI bridge (Phase 2.5).
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*
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* Provides:
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* - low-level JTAG primitives (set_ir, shift_dr, idle_cycles) that
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* operate directly on jc->io_functions, leaving jtag_core untouched;
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* - bitstream loading via CFG_IN to install a BSCAN proxy in the FPGA
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* fabric;
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* - a fast SPI transfer routine via USER1 once the proxy is loaded.
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*
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* Current assumption: single device on the JTAG chain. Multi-device
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* support requires knowing the IR length of bypassed devices; defer.
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*
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* The SPI transfer entry point is wired against the quartiq jtagspi
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* proxy convention but the protocol header still needs to be confirmed
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* against an actual proxy bitstream (see openocd src/flash/nor/jtagspi.c).
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*/
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#include <stddef.h>
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#include <stdint.h>
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#include "jtag_core/jtag_core.h"
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#include "fpga/fpga.h"
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/* --- Low-level primitives (single-device chain) -------------------- */
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/* Shift `opcode` into IR. `ir_length` is the IR width in bits. */
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int bscan_set_ir(jtag_core *jc, unsigned int opcode, int ir_length);
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/* Shift `nbits` through DR. `tdi` may be NULL (shifts zeros).
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* `tdo` may be NULL (write only). Both buffers are LSB-first per byte. */
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int bscan_shift_dr(jtag_core *jc, const uint8_t *tdi, uint8_t *tdo, int nbits);
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/* Emit `ncycles` TCK cycles while staying in Run-Test/Idle. */
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int bscan_idle_cycles(jtag_core *jc, int ncycles);
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/* --- High-level operations ---------------------------------------- */
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/* Load a raw bitstream payload (no .bit container header) into the
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* FPGA via JPROGRAM -> CFG_IN -> shift -> JSTART. Bit-reverses each
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* byte before shifting (Xilinx convention). */
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int bscan_load_bitstream(jtag_core *jc, const fpga_target *t,
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const uint8_t *data, size_t nbytes);
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/* Convenience wrapper: read a file and load it. Detects the Xilinx
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* .bit header and skips it; otherwise treats the file as raw payload. */
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int bscan_load_bitstream_file(jtag_core *jc, const fpga_target *t,
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const char *path);
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/* Transfer `nbytes` of SPI data through the BSCAN proxy (USER1 DR).
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* Placeholder: protocol details deferred until an actual proxy
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* bitstream is available for testing. */
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int bscan_spi_xfer(jtag_core *jc, const fpga_target *t,
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const uint8_t *tx, uint8_t *rx, size_t nbytes);
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#endif
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@@ -38,6 +38,7 @@
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#include "bsdl_parser/bsdl_loader.h"
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#include "os_interface/os_interface.h"
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#include "fpga/fpga.h"
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#include "bscan_spi/bscan_spi.h"
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#include "env.h"
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@@ -2793,6 +2794,116 @@ static int cmd_fpga_info(script_ctx *ctx, char *line)
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return JTAG_CORE_NO_ERROR;
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}
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const char *cmd_bscan_set_ir_help[] = {
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"<opcode_hex> <ir_length>",
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"Shifts <opcode_hex> into the IR (single-device chain).",
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"Useful for testing the low-level JTAG primitives.",
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""};
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static int cmd_bscan_set_ir(script_ctx *ctx, char *line)
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{
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char op_txt[DEFAULT_BUFLEN];
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char len_txt[DEFAULT_BUFLEN];
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unsigned int opcode;
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int ir_length, ret;
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jtag_core *jc = (jtag_core *)ctx->app_ctx;
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if (get_param(ctx, line, 1, op_txt) < 0 || get_param(ctx, line, 2, len_txt) < 0) {
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ctx->script_printf(ctx, MSG_ERROR, "Usage: bscan_set_ir <opcode_hex> <ir_length>\n");
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return JTAG_CORE_BAD_PARAMETER;
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}
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opcode = (unsigned int)strtoul(op_txt, NULL, 16);
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ir_length = (int)strtoul(len_txt, NULL, 0);
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ret = bscan_set_ir(jc, opcode, ir_length);
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if (ret < 0) {
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ctx->script_printf(ctx, MSG_ERROR, "bscan_set_ir failed (%d)\n", ret);
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return JTAG_CORE_IO_ERROR;
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}
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ctx->script_printf(ctx, MSG_INFO_0, "IR <- 0x%X (%d bits)\n", opcode, ir_length);
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return JTAG_CORE_NO_ERROR;
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}
|
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|
||||
const char *cmd_bscan_shift_dr_help[] = {
|
||||
"<nbits>",
|
||||
"Shifts <nbits> zeros into DR, prints the captured TDO in hex (LSB first).",
|
||||
"Run after bscan_set_ir to read a register (e.g. IDCODE -> shift 32 bits).",
|
||||
""};
|
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static int cmd_bscan_shift_dr(script_ctx *ctx, char *line)
|
||||
{
|
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char nb_txt[DEFAULT_BUFLEN];
|
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int nbits, nbytes, i, ret;
|
||||
uint8_t *tdo;
|
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jtag_core *jc = (jtag_core *)ctx->app_ctx;
|
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|
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if (get_param(ctx, line, 1, nb_txt) < 0) {
|
||||
ctx->script_printf(ctx, MSG_ERROR, "Usage: bscan_shift_dr <nbits>\n");
|
||||
return JTAG_CORE_BAD_PARAMETER;
|
||||
}
|
||||
nbits = (int)strtoul(nb_txt, NULL, 0);
|
||||
if (nbits <= 0 || nbits > 8 * DEFAULT_BUFLEN) {
|
||||
ctx->script_printf(ctx, MSG_ERROR, "Invalid nbits\n");
|
||||
return JTAG_CORE_BAD_PARAMETER;
|
||||
}
|
||||
nbytes = (nbits + 7) / 8;
|
||||
tdo = calloc(1, (size_t)nbytes);
|
||||
if (!tdo) return JTAG_CORE_MEM_ERROR;
|
||||
|
||||
ret = bscan_shift_dr(jc, NULL, tdo, nbits);
|
||||
if (ret < 0) {
|
||||
free(tdo);
|
||||
ctx->script_printf(ctx, MSG_ERROR, "bscan_shift_dr failed (%d)\n", ret);
|
||||
return JTAG_CORE_IO_ERROR;
|
||||
}
|
||||
ctx->script_printf(ctx, MSG_INFO_0, "DR =");
|
||||
for (i = nbytes - 1; i >= 0; i--) {
|
||||
ctx->script_printf(ctx, MSG_NONE, " %.2X", tdo[i]);
|
||||
}
|
||||
ctx->script_printf(ctx, MSG_NONE, "\n");
|
||||
free(tdo);
|
||||
return JTAG_CORE_NO_ERROR;
|
||||
}
|
||||
|
||||
const char *cmd_bscan_load_bitstream_help[] = {
|
||||
"<device> <path>",
|
||||
"Loads a bitstream (.bit or raw .bin) into device <device> via JPROGRAM/CFG_IN/JSTART.",
|
||||
"Device must be matched in the FPGA registry (run fpga_info to check).",
|
||||
""};
|
||||
static int cmd_bscan_load_bitstream(script_ctx *ctx, char *line)
|
||||
{
|
||||
char dev_txt[DEFAULT_BUFLEN];
|
||||
char path[DEFAULT_BUFLEN];
|
||||
int device, ret;
|
||||
unsigned long idcode;
|
||||
const fpga_target *t;
|
||||
jtag_core *jc = (jtag_core *)ctx->app_ctx;
|
||||
|
||||
if (get_param(ctx, line, 1, dev_txt) < 0 || get_param(ctx, line, 2, path) < 0) {
|
||||
ctx->script_printf(ctx, MSG_ERROR, "Usage: bscan_load_bitstream <device> <path>\n");
|
||||
return JTAG_CORE_BAD_PARAMETER;
|
||||
}
|
||||
device = (int)strtoul(dev_txt, NULL, 0);
|
||||
|
||||
if (jtagcore_get_number_of_devices(jc) <= 0) {
|
||||
ctx->script_printf(ctx, MSG_ERROR, "No device on the chain. Run jtag_autoinit first.\n");
|
||||
return JTAG_CORE_NOT_FOUND;
|
||||
}
|
||||
idcode = jtagcore_get_dev_id(jc, device);
|
||||
t = fpga_lookup_by_idcode(idcode);
|
||||
if (!t) {
|
||||
ctx->script_printf(ctx, MSG_ERROR, "Device %d IDCODE 0x%.8lX not in FPGA registry\n", device, idcode);
|
||||
return JTAG_CORE_NOT_FOUND;
|
||||
}
|
||||
|
||||
ctx->script_printf(ctx, MSG_INFO_0, "Loading %s on device %d (%s)...\n", path, device, t->name);
|
||||
ret = bscan_load_bitstream_file(jc, t, path);
|
||||
if (ret < 0) {
|
||||
ctx->script_printf(ctx, MSG_ERROR, "bscan_load_bitstream_file failed (%d)\n", ret);
|
||||
return JTAG_CORE_IO_ERROR;
|
||||
}
|
||||
ctx->script_printf(ctx, MSG_INFO_0, "Bitstream loaded.\n");
|
||||
return JTAG_CORE_NO_ERROR;
|
||||
}
|
||||
|
||||
cmd_list script_commands_list[] =
|
||||
{
|
||||
{"print", cmd_print, cmd_print_help},
|
||||
@@ -2837,6 +2948,9 @@ cmd_list script_commands_list[] =
|
||||
{"jtag_spi_rd_wr", cmd_spi_rd_wr, cmd_spi_rd_wr_help},
|
||||
{"fpga_list", cmd_fpga_list, cmd_fpga_list_help},
|
||||
{"fpga_info", cmd_fpga_info, cmd_fpga_info_help},
|
||||
{"bscan_set_ir", cmd_bscan_set_ir, cmd_bscan_set_ir_help},
|
||||
{"bscan_shift_dr", cmd_bscan_shift_dr, cmd_bscan_shift_dr_help},
|
||||
{"bscan_load_bitstream", cmd_bscan_load_bitstream, cmd_bscan_load_bitstream_help},
|
||||
{0, 0}};
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
Reference in New Issue
Block a user