François
3579c5efb0
- registry moves from the array in fpga.c to fpga_registry.yaml at the repo root, parsed via libyaml (pkg-config yaml-0.1); adding a part is now a YAML edit, no rebuild - looked up CWD-relative (like bsdl_files/), overridable with $BS_FPGA_REGISTRY, loaded lazily once; public API unchanged - fpga_list shows the source file (fpga_registry_source()) - add microsemi_igloo2/smartfusion2 and lattice_machxo2/3 families, ready for the non-Xilinx targets - docs updated: CLAUDE.md, README, tutorial "add a target" walkthrough Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
69 lines
2.5 KiB
C
69 lines
2.5 KiB
C
#ifndef _FPGA_H
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#define _FPGA_H
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/*
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* Per-target FPGA descriptor and registry.
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*
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* Holds the facts that cannot be derived from the BSDL alone:
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* - IDCODE pattern to match on the chain
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* - private IR opcodes (USER1, CFG_IN, JPROGRAM, …) needed for
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* configuration and for the BSCAN proxy bridge (Phase 2.5)
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* - path to the BSCAN proxy bitstream
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* - per-target caveats (known hardware gotchas)
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*
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* The registry is loaded at runtime from a YAML file (no longer a
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* compile-time array). Adding an FPGA = one entry in the YAML +
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* its .bsd in bsdl_files/ + (optionally) its proxy .bit in
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* bscan_proxies/. See fpga_registry.yaml for the format.
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*/
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#include "jtag_core/jtag_core.h"
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typedef enum {
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FPGA_FAMILY_UNKNOWN = 0,
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FPGA_FAMILY_XILINX_7,
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FPGA_FAMILY_XILINX_US,
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FPGA_FAMILY_XILINX_USP,
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FPGA_FAMILY_MICROSEMI_IGLOO2,
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FPGA_FAMILY_MICROSEMI_SMARTFUSION2,
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FPGA_FAMILY_LATTICE_MACHXO2,
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FPGA_FAMILY_LATTICE_MACHXO3,
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} fpga_family;
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/* Caveat flags: known hardware gotchas for a part. */
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#define FPGA_CAVEAT_CCLK_VIA_STARTUP (1u << 0) /* CCLK not directly drivable in EXTEST */
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typedef struct {
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const char *name; /* human-readable part name */
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unsigned long idcode; /* IDCODE pattern */
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unsigned long idcode_mask; /* bits to ignore (typically 0x0FFFFFFF for Xilinx — version masked) */
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fpga_family family;
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const char *bsdl_filename; /* basename within bsdl_files/ */
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int ir_length; /* IR width in bits */
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/* Private IR opcodes (0 = N/A for this family).
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* For Xilinx, these are read from the BSDL INSTRUCTION_OPCODE block. */
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unsigned int ir_cfg_in;
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unsigned int ir_user1;
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unsigned int ir_jprogram;
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unsigned int ir_jstart;
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unsigned int ir_jshutdown;
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unsigned int ir_isc_disable;
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const char *proxy_bitstream; /* path under bscan_proxies/, NULL if not yet available */
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unsigned int caveats; /* FPGA_CAVEAT_* flags */
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} fpga_target;
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/* Registry access. The YAML file is loaded lazily on first call to any
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* of these, and cached for the process lifetime. */
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int fpga_get_target_count(void);
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const fpga_target * fpga_get_target_by_index(int index);
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const fpga_target * fpga_lookup_by_idcode(unsigned long idcode);
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const char * fpga_family_name(fpga_family f);
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/* Path the registry was loaded from, or NULL if nothing loaded
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* (file missing / parse error). For diagnostics. */
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const char * fpga_registry_source(void);
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#endif
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