From d6b5fb572fcf8605b35342f0cd9ab373c4ba5f30 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fran=C3=A7ois?= Date: Sun, 24 May 2026 01:04:44 +0200 Subject: [PATCH] doc: how to build a not-pre-built proxy (KU15P) in the tutorial quartiq ships no UltraScale+ proxy, so the KU15P .bit must be built from xilinx_bscan_spi.py (Migen + Vivado) after adding the part to the generator's device table. Put the operational steps in the tutorial's Phase 2.5 (where users look for a bitstream); CLAUDE.md just points to it. --- CLAUDE.md | 5 +++-- doc/tutorial.md | 23 +++++++++++++++++++++++ 2 files changed, 26 insertions(+), 2 deletions(-) diff --git a/CLAUDE.md b/CLAUDE.md index 9021b76..9b241b5 100644 --- a/CLAUDE.md +++ b/CLAUDE.md @@ -124,8 +124,9 @@ then `JSTART` and check `DONE`. ## External references - **BSCAN proxy bitstreams**: `quartiq/bscan_spi_bitstreams` (MIT). - Pre-built `.bit` for most Xilinx parts; Migen sources to rebuild any - part that's missing (needs Vivado). + Pre-built `.bit` for many Xilinx parts; Migen sources to rebuild any + part that's missing (needs Vivado). Building a proxy that isn't + pre-built (e.g. the KU15P) is covered in `doc/tutorial.md`, Phase 2.5. - **Reference host-side implementation**: `openocd/src/flash/nor/jtagspi.c`. Defines the proxy protocol (header with bit count + CS state, then payload). Don't reinvent — match what OpenOCD does so we share the diff --git a/doc/tutorial.md b/doc/tutorial.md index 0811d49..70e9db1 100644 --- a/doc/tutorial.md +++ b/doc/tutorial.md @@ -281,6 +281,29 @@ curl -L -o bscan_proxies/bscan_spi_xcku040.bit \ The registry entry for the part points at this file via its `proxy_bitstream` field (e.g. the XCKU040 entry → `bscan_spi_xcku040.bit`). +#### When your part isn't pre-built (e.g. the KU15P) + +quartiq ships `.bit` only for the parts its generator knows — it has +**no UltraScale+** proxy (its single UltraScale entry is the KU040), so +the KU15P has to be built from source. You need (o)Migen + Vivado +(2022.2; ISE 14.7 for older parts). From a clone of the quartiq repo, +per its README: + +```sh +python3 -m venv --system-site-packages .venv +./.venv/bin/pip install -r requirements.txt +PATH=$PATH:/opt/Xilinx/Vivado/2022.2/bin \ + ./.venv/bin/python3 xilinx_bscan_spi.py ... +``` + +The XCKU15P first has to be **added to the generator's device table** +(a Migen platform entry) — it's not just a command-line part flag. + +Once built, drop `bscan_spi_xcku15p.bit` into `bscan_proxies/` (it's +MIT, like the KU040 — keep `bscan_proxies/LICENSE.quartiq`) and set the +`proxy_bitstream` field on the KU15P entry in `modules/fpga/fpga.c` +(currently `NULL`). + ### Load the bridge and talk SPI ```