restructure: code+libs under src/, runtime resources under data/

Separate the two concerns the repo root was mixing:
- src/   — bs/, modules/, libs/ (code + vendored libs)
- data/  — fpga_registry.yaml, probes.yaml, bsdl_files/, bscan_proxies/,
           scripts/ (everything the tool reads at runtime, CWD-relative)
- doc/   — kept at the root

CMake: repoint DIR_MODULES/DIR_LIBS and add_subdirectory at src/; emit
the binary at the build/ root (build/bs) via CMAKE_RUNTIME_OUTPUT_DIRECTORY
instead of the nested build/src/bs/. The jtag_core ../../libs path still
resolves since modules and libs moved together.

Runtime default paths now point under data/ (fpga.c, probes.c, script.c
bsdl_files lookup, init.c config.script). Docs (README/tutorial/CLAUDE)
updated for the new layout, src/ module paths, and ./build/bs.

Validated on the IGLOO2/FlashPro: profiles, autoinit, and svf_play all
work run from the repo root.

Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>

data/bscan_proxies/LICENSE.quartiq

@@ -0,0 +1,21 @@
+MIT License
+
+Copyright (c) 2015-2021 QUARTIQ GmbH
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.

data/bscan_proxies/README.md

@@ -0,0 +1,18 @@
+# BSCAN proxy bitstreams
+
+Pre-built "BSCAN proxy" bitstreams that bridge the JTAG `USER1`
+instruction to an FPGA's SPI flash pins (via a `BSCANE2` primitive),
+enabling fast SPI flashing — see `doc/tutorial.md`, Phase 2.5.
+
+These `.bit` files are **not** built here. They come from
+[quartiq/bscan_spi_bitstreams](https://github.com/quartiq/bscan_spi_bitstreams),
+© QUARTIQ GmbH, MIT-licensed — see `LICENSE.quartiq`. The host-side
+framing in `src/modules/bscan/` matches OpenOCD's `jtagspi` so the same
+bitstreams work.
+
+| File | Part | Used by |
+|------|------|---------|
+| `bscan_spi_xcku040.bit` | Xilinx Kintex UltraScale XCKU040 | KCU105 |
+
+To add another part, drop the matching `bscan_spi_<part>.bit` here and
+point the registry entry's `proxy_bitstream` field at it.

data/fpga_registry.yaml

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+# bs_explorer FPGA registry
+#
+# Loaded at runtime by modules/fpga/. Looked up relative to the current
+# directory (run bs_explorer from the repo root), or via $BS_FPGA_REGISTRY.
+#
+# One entry per programmable device. Fields:
+#   name              human-readable part name (quoted)
+#   idcode            JTAG IDCODE pattern (hex)
+#   idcode_mask       bits compared when matching (0x0FFFFFFF on Xilinx
+#                     masks the version nibble); default 0xFFFFFFFF
+#   family            xilinx_7 | xilinx_us | xilinx_usp |
+#                     microsemi_igloo2 | microsemi_smartfusion2 |
+#                     lattice_machxo2 | lattice_machxo3
+#   bsdl              basename of the .bsd in bsdl_files/
+#   ir_length         IR width in bits
+#   ir_cfg_in / ir_user1 / ir_jprogram / ir_jstart / ir_jshutdown /
+#   ir_isc_disable    private IR opcodes (hex; from the BSDL on Xilinx)
+#   proxy_bitstream   basename of the proxy .bit in bscan_proxies/
+#                     (omit if none is available yet)
+#   caveats           space/comma-separated flags: cclk_via_startup
+#                     (omit if none)
+#   max_tck_khz       max safe JTAG TCK in kHz for this part/board; if the
+#                     requested clock exceeds it, jtag_autoinit clamps and
+#                     re-opens at the cap (omit / 0 = unspecified)
+#   prog              programming backend: proxy_spi | svf | none. Omit to
+#                     infer (proxy_bitstream -> proxy_spi; Microsemi/Lattice
+#                     -> svf; else none).
+
+fpgas:
+  # Xilinx Kintex UltraScale+ XCKU15P
+  # IDCODE / opcodes from bsdl_files/xcku15p_ffve1517.bsd, IR length 6.
+  - name:           "Xilinx Kintex UltraScale+ XCKU15P"
+    idcode:         0x04A56093
+    idcode_mask:    0x0FFFFFFF
+    family:         xilinx_usp
+    bsdl:           xcku15p_ffve1517.bsd
+    ir_length:      6
+    ir_cfg_in:      0x05
+    ir_user1:       0x02
+    ir_jprogram:    0x0B
+    ir_jstart:      0x0C
+    ir_jshutdown:   0x0D
+    ir_isc_disable: 0x16
+    caveats:        cclk_via_startup
+    prog:           proxy_spi
+    # proxy_bitstream not yet built for this part (see doc/tutorial.md, Phase 2.5)
+
+  # Xilinx Kintex UltraScale XCKU040 (KCU105 eval board)
+  # IDCODE / opcodes from bsdl_files/xcku040_ffva1156.bsd, IR length 6.
+  - name:            "Xilinx Kintex UltraScale XCKU040"
+    idcode:          0x03822093
+    idcode_mask:     0x0FFFFFFF
+    family:          xilinx_us
+    bsdl:            xcku040_ffva1156.bsd
+    ir_length:       6
+    ir_cfg_in:       0x05
+    ir_user1:        0x02
+    ir_jprogram:     0x0B
+    ir_jstart:       0x0C
+    ir_jshutdown:    0x0D
+    ir_isc_disable:  0x16
+    proxy_bitstream: bscan_spi_xcku040.bit
+    caveats:         cclk_via_startup
+    prog:            proxy_spi
+
+  # Microsemi IGLOO2 M2GL010T (M2GL-EVAL-KIT)
+  # IDCODE / IR length from bsdl_files/m2gl010t-fg484.bsd
+  #   IDCODE_REGISTER "XXXX1111100000000011000111001111" -> 0x0F8031CF
+  #   (top nibble = silicon revision, masked off). Shared die with the
+  #   SmartFusion2 M2S010, so both report the same IDCODE.
+  # No proxy: IGLOO2 internal flash is programmed by playing an SVF
+  # exported from Libero (SVF player not yet implemented), not via the
+  # Xilinx BSCAN-proxy SPI path — so the ir_*/proxy fields don't apply.
+  - name:           "Microsemi IGLOO2 M2GL010T"
+    idcode:         0x0F8031CF
+    idcode_mask:    0x0FFFFFFF
+    family:         microsemi_igloo2
+    bsdl:           m2gl010t-fg484.bsd
+    ir_length:      8
+    prog:           svf

data/probes.yaml

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+# bs_explorer probe-config profiles
+#
+# Loaded at runtime by modules/probes/, layered on top of the built-in
+# config.script defaults. Looked up CWD-relative (run from the repo
+# root), or via $BS_PROBES.
+#
+#   defaults:  applied on every `jtag_open` (restores a known baseline
+#              so opening without a profile is deterministic).
+#   profiles:  named override sets; select with `jtag_open <idx> <name>`.
+#
+# Each key is a probe variable (see modules/config/config.script for the
+# full list); each value is what `set <KEY> <value>` would assign.
+
+defaults:
+  # Baseline for a standalone FT2232H JTAG probe: drive ADBUS4 as the
+  # "JTAG buffer enable" output (matches the built-in default).
+  PROBE_FTDI_SET_PIN_DIR_ADBUS4: 1
+  # Driver-neutral JTAG clock in kHz. Honoured by the FTDI driver (mapped
+  # to PROBE_FTDI_TCK_FREQ_KHZ at open) and our Digilent driver. Leave it
+  # out to keep each driver's own default (FTDI 1000, Digilent 4000).
+  # JTAG_TCK_FREQ_KHZ: 1000
+
+profiles:
+  # Embedded FlashPro on Microsemi eval kits (FT4232H, JTAG on channel A
+  # = probe index 0). Its ADBUS4 must be left high-Z or the chain stays
+  # silent. Usage: jtag_open 0 flashpro
+  flashpro:
+    PROBE_FTDI_SET_PIN_DIR_ADBUS4: 0
+
+  # Plain FT2232H probe: nothing to override beyond the defaults.
+  ft2232h: {}

data/scripts/example_script.txt

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+
+jtag_open 0
+jtag_autoinit
+jtag_mode 0 EXTEST