François
d1bdce91dc
Separate the two concerns the repo root was mixing:
- src/ — bs/, modules/, libs/ (code + vendored libs)
- data/ — fpga_registry.yaml, probes.yaml, bsdl_files/, bscan_proxies/,
scripts/ (everything the tool reads at runtime, CWD-relative)
- doc/ — kept at the root
CMake: repoint DIR_MODULES/DIR_LIBS and add_subdirectory at src/; emit
the binary at the build/ root (build/bs) via CMAKE_RUNTIME_OUTPUT_DIRECTORY
instead of the nested build/src/bs/. The jtag_core ../../libs path still
resolves since modules and libs moved together.
Runtime default paths now point under data/ (fpga.c, probes.c, script.c
bsdl_files lookup, init.c config.script). Docs (README/tutorial/CLAUDE)
updated for the new layout, src/ module paths, and ./build/bs.
Validated on the IGLOO2/FlashPro: profiles, autoinit, and svf_play all
work run from the repo root.
Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
81 lines
3.4 KiB
YAML
81 lines
3.4 KiB
YAML
# bs_explorer FPGA registry
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#
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# Loaded at runtime by modules/fpga/. Looked up relative to the current
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# directory (run bs_explorer from the repo root), or via $BS_FPGA_REGISTRY.
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#
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# One entry per programmable device. Fields:
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# name human-readable part name (quoted)
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# idcode JTAG IDCODE pattern (hex)
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# idcode_mask bits compared when matching (0x0FFFFFFF on Xilinx
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# masks the version nibble); default 0xFFFFFFFF
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# family xilinx_7 | xilinx_us | xilinx_usp |
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# microsemi_igloo2 | microsemi_smartfusion2 |
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# lattice_machxo2 | lattice_machxo3
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# bsdl basename of the .bsd in bsdl_files/
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# ir_length IR width in bits
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# ir_cfg_in / ir_user1 / ir_jprogram / ir_jstart / ir_jshutdown /
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# ir_isc_disable private IR opcodes (hex; from the BSDL on Xilinx)
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# proxy_bitstream basename of the proxy .bit in bscan_proxies/
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# (omit if none is available yet)
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# caveats space/comma-separated flags: cclk_via_startup
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# (omit if none)
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# max_tck_khz max safe JTAG TCK in kHz for this part/board; if the
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# requested clock exceeds it, jtag_autoinit clamps and
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# re-opens at the cap (omit / 0 = unspecified)
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# prog programming backend: proxy_spi | svf | none. Omit to
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# infer (proxy_bitstream -> proxy_spi; Microsemi/Lattice
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# -> svf; else none).
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fpgas:
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# Xilinx Kintex UltraScale+ XCKU15P
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# IDCODE / opcodes from bsdl_files/xcku15p_ffve1517.bsd, IR length 6.
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- name: "Xilinx Kintex UltraScale+ XCKU15P"
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idcode: 0x04A56093
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idcode_mask: 0x0FFFFFFF
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family: xilinx_usp
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bsdl: xcku15p_ffve1517.bsd
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ir_length: 6
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ir_cfg_in: 0x05
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ir_user1: 0x02
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ir_jprogram: 0x0B
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ir_jstart: 0x0C
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ir_jshutdown: 0x0D
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ir_isc_disable: 0x16
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caveats: cclk_via_startup
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prog: proxy_spi
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# proxy_bitstream not yet built for this part (see doc/tutorial.md, Phase 2.5)
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# Xilinx Kintex UltraScale XCKU040 (KCU105 eval board)
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# IDCODE / opcodes from bsdl_files/xcku040_ffva1156.bsd, IR length 6.
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- name: "Xilinx Kintex UltraScale XCKU040"
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idcode: 0x03822093
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idcode_mask: 0x0FFFFFFF
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family: xilinx_us
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bsdl: xcku040_ffva1156.bsd
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ir_length: 6
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ir_cfg_in: 0x05
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ir_user1: 0x02
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ir_jprogram: 0x0B
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ir_jstart: 0x0C
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ir_jshutdown: 0x0D
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ir_isc_disable: 0x16
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proxy_bitstream: bscan_spi_xcku040.bit
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caveats: cclk_via_startup
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prog: proxy_spi
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# Microsemi IGLOO2 M2GL010T (M2GL-EVAL-KIT)
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# IDCODE / IR length from bsdl_files/m2gl010t-fg484.bsd
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# IDCODE_REGISTER "XXXX1111100000000011000111001111" -> 0x0F8031CF
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# (top nibble = silicon revision, masked off). Shared die with the
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# SmartFusion2 M2S010, so both report the same IDCODE.
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# No proxy: IGLOO2 internal flash is programmed by playing an SVF
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# exported from Libero (SVF player not yet implemented), not via the
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# Xilinx BSCAN-proxy SPI path — so the ir_*/proxy fields don't apply.
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- name: "Microsemi IGLOO2 M2GL010T"
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idcode: 0x0F8031CF
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idcode_mask: 0x0FFFFFFF
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family: microsemi_igloo2
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bsdl: m2gl010t-fg484.bsd
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ir_length: 8
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prog: svf
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