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fpga: add XCKU040 (KCU105) registry entry

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IDCODE 0x03822093, UltraScale, opcodes from xcku040_ffva1156.bsd
(same as the family: USER1 0x02, CFG_IN 0x05, JPROGRAM 0x0B,
JSTART 0x0C). Points proxy_bitstream at bscan_spi_xcku040.bit.
This commit is contained in:
Foué
2026-05-23 17:16:19 +02:00
parent 952c010c63
commit ba9372c8b2
1 changed files with 20 additions and 0 deletions
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20
modules/fpga/fpga.c
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@@ -23,6 +23,26 @@ static const fpga_target fpga_registry[] = {
.proxy_bitstream = NULL, /* TODO Phase 2.5: bscan_spi_xcku15p.bit */ .proxy_bitstream = NULL, /* TODO Phase 2.5: bscan_spi_xcku15p.bit */
.quirks = FPGA_QUIRK_CCLK_VIA_STARTUP, .quirks = FPGA_QUIRK_CCLK_VIA_STARTUP,
}, },
/* Xilinx Kintex UltraScale XCKU040 (KCU105 eval board)
* IDCODE_REGISTER and INSTRUCTION_OPCODE values come from
* bsdl_files/xcku040_ffva1156.bsd
* IR length 6 bits, version nibble (bits 31:28) ignored. */
{
.name = "Xilinx Kintex UltraScale XCKU040",
.idcode = 0x03822093,
.idcode_mask = 0x0FFFFFFF,
.family = FPGA_FAMILY_XILINX_US,
.bsdl_filename = "xcku040_ffva1156.bsd",
.ir_length = 6,
.ir_cfg_in = 0x05,
.ir_user1 = 0x02,
.ir_jprogram = 0x0B,
.ir_jstart = 0x0C,
.ir_jshutdown = 0x0D,
.ir_isc_disable = 0x16,
.proxy_bitstream = "bscan_spi_xcku040.bit",
.quirks = FPGA_QUIRK_CCLK_VIA_STARTUP,
},
}; };
#define FPGA_REGISTRY_LEN ((int)(sizeof(fpga_registry) / sizeof(fpga_registry[0]))) #define FPGA_REGISTRY_LEN ((int)(sizeof(fpga_registry) / sizeof(fpga_registry[0])))