From ba9372c8b2803f0c1c39cbc5bfa2897a9ac62d96 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fran=C3=A7ois?= Date: Sat, 23 May 2026 17:16:19 +0200 Subject: [PATCH] fpga: add XCKU040 (KCU105) registry entry IDCODE 0x03822093, UltraScale, opcodes from xcku040_ffva1156.bsd (same as the family: USER1 0x02, CFG_IN 0x05, JPROGRAM 0x0B, JSTART 0x0C). Points proxy_bitstream at bscan_spi_xcku040.bit. --- modules/fpga/fpga.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/modules/fpga/fpga.c b/modules/fpga/fpga.c index f5087ce..4639600 100644 --- a/modules/fpga/fpga.c +++ b/modules/fpga/fpga.c @@ -23,6 +23,26 @@ static const fpga_target fpga_registry[] = { .proxy_bitstream = NULL, /* TODO Phase 2.5: bscan_spi_xcku15p.bit */ .quirks = FPGA_QUIRK_CCLK_VIA_STARTUP, }, + /* Xilinx Kintex UltraScale XCKU040 (KCU105 eval board) + * IDCODE_REGISTER and INSTRUCTION_OPCODE values come from + * bsdl_files/xcku040_ffva1156.bsd + * IR length 6 bits, version nibble (bits 31:28) ignored. */ + { + .name = "Xilinx Kintex UltraScale XCKU040", + .idcode = 0x03822093, + .idcode_mask = 0x0FFFFFFF, + .family = FPGA_FAMILY_XILINX_US, + .bsdl_filename = "xcku040_ffva1156.bsd", + .ir_length = 6, + .ir_cfg_in = 0x05, + .ir_user1 = 0x02, + .ir_jprogram = 0x0B, + .ir_jstart = 0x0C, + .ir_jshutdown = 0x0D, + .ir_isc_disable = 0x16, + .proxy_bitstream = "bscan_spi_xcku040.bit", + .quirks = FPGA_QUIRK_CCLK_VIA_STARTUP, + }, }; #define FPGA_REGISTRY_LEN ((int)(sizeof(fpga_registry) / sizeof(fpga_registry[0])))