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fpga: rename "quirk" to "caveat"

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"quirk" was unclear jargon; "caveat" matches the wording already used in
the README/CLAUDE.md ("Xilinx caveats"). Renames the struct field, the
FPGA_QUIRK_* macro, the fpga_info output and the docs. No behaviour
change.
This commit is contained in:
Foué
2026-05-24 00:31:47 +02:00
parent 35b2022362
commit 71b74fa03d
5 changed files with 16 additions and 16 deletions
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4
modules/fpga/fpga.c
View File

@@ -21,7 +21,7 @@ static const fpga_target fpga_registry[] = {
.ir_jshutdown = 0x0D,
.ir_isc_disable = 0x16,
.proxy_bitstream = NULL, /* TODO Phase 2.5: bscan_spi_xcku15p.bit */
.quirks = FPGA_QUIRK_CCLK_VIA_STARTUP,
.caveats = FPGA_CAVEAT_CCLK_VIA_STARTUP,
},
/* Xilinx Kintex UltraScale XCKU040 (KCU105 eval board)
* IDCODE_REGISTER and INSTRUCTION_OPCODE values come from
@@ -41,7 +41,7 @@ static const fpga_target fpga_registry[] = {
.ir_jshutdown = 0x0D,
.ir_isc_disable = 0x16,
.proxy_bitstream = "bscan_spi_xcku040.bit",
.quirks = FPGA_QUIRK_CCLK_VIA_STARTUP,
.caveats = FPGA_CAVEAT_CCLK_VIA_STARTUP,
},
};

8
modules/fpga/fpga.h
View File

@@ -9,7 +9,7 @@
* - private IR opcodes (USER1, CFG_IN, JPROGRAM, …) needed for
* configuration and for the BSCAN proxy bridge (Phase 2.5)
* - path to the BSCAN proxy bitstream
* - per-target quirks
* - per-target caveats (known hardware gotchas)
*
* Adding an FPGA = one entry in fpga_registry[] + its .bsd in
* bsdl_files/ + (optionally) its proxy .bit in bscan_proxies/.
@@ -24,8 +24,8 @@ typedef enum {
FPGA_FAMILY_XILINX_USP,
} fpga_family;
/* Quirk flags */
#define FPGA_QUIRK_CCLK_VIA_STARTUP (1u << 0) /* CCLK not directly drivable in EXTEST */
/* Caveat flags: known hardware gotchas for a part. */
#define FPGA_CAVEAT_CCLK_VIA_STARTUP (1u << 0) /* CCLK not directly drivable in EXTEST */
typedef struct {
const char *name; /* human-readable part name */
@@ -45,7 +45,7 @@ typedef struct {
unsigned int ir_isc_disable;
const char *proxy_bitstream; /* path under bscan_proxies/, NULL if not yet available */
unsigned int quirks;
unsigned int caveats; /* FPGA_CAVEAT_* flags */
} fpga_target;
/* Registry access */

8
modules/script/script.c
View File

@@ -2795,10 +2795,10 @@ static int cmd_fpga_list(script_ctx *ctx, char *line)
i, t->idcode, t->idcode_mask,
t->name, fpga_family_name(t->family));
ctx->script_printf(ctx, MSG_NONE,
" bsdl=%s ir=%d proxy=%s quirks=0x%x\n",
" bsdl=%s ir=%d proxy=%s caveats=0x%x\n",
t->bsdl_filename, t->ir_length,
t->proxy_bitstream ? t->proxy_bitstream : "(none yet)",
t->quirks);
t->caveats);
}
return JTAG_CORE_NO_ERROR;
}
@@ -2831,9 +2831,9 @@ static int cmd_fpga_info(script_ctx *ctx, char *line)
ctx->script_printf(ctx, MSG_INFO_0,
"Device %d IDCODE 0x%.8lX -> %s [%s]\n",
i, idcode, t->name, fpga_family_name(t->family));
if (t->quirks & FPGA_QUIRK_CCLK_VIA_STARTUP) {
if (t->caveats & FPGA_CAVEAT_CCLK_VIA_STARTUP) {
ctx->script_printf(ctx, MSG_NONE,
" quirk: CCLK routed via STARTUP primitive (not drivable in EXTEST)\n");
" caveat: CCLK routed via STARTUP primitive (not drivable in EXTEST)\n");
}
} else {
ctx->script_printf(ctx, MSG_INFO_0,