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arm_debug: doc - memory read validated by 32 KB flash dump

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cpu_read dumped the LPC2103's full 32 KB flash to Intel HEX
(objcopy-verified: all records/checksums valid, correct vectors). Update
the comments to reflect the working state and the power-on -> one halt ->
dump flow (context save/restore for repeated reads is the next step).

Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
This commit is contained in:
Foué
2026-05-24 20:23:04 +02:00
parent cdbeea7b61
commit 44cb9dfbae
1 changed files with 12 additions and 12 deletions
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24
src/modules/arm_debug/arm_debug.c
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@@ -17,14 +17,14 @@
* use "quiet" ops that never enter Run-Test/Idle (so they don't clock * use "quiet" ops that never enter Run-Test/Idle (so they don't clock
* the core and clobber loaded registers), and the sys-speed poll * the core and clobber loaded registers), and the sys-speed poll
* drives the access one clock at a time, stopping the instant * drives the access one clock at a time, stopping the instant
* SYSCOMP appears. Validated by reading the LPC2103 reset vectors and * SYSCOMP appears. Validated by dumping the LPC2103's full 32 KB
* contiguous multi-block code. * flash to Intel HEX (objcopy-verified, correct vectors + code).
* - WIP: reliability across halt states. The first read after certain * - caveat: the read clobbers r0..r14 and there is no context
* halts can time out (sys-speed never reaches SYSCOMP), which leaves * save/restore, so the intended flow is power-on -> one halt -> dump.
* the core running free; subsequent reads in the same halt are * Repeated halt/read cycles without a power-cycle degrade (a later
* consistent and correct. Needs a deterministic pre-read pipeline * re-halt of the clobbered core is messy and may time out).
* normalization for every halt state. See arm7-debug-dclk-timing. * - todo: context save/restore (clean resume + repeated reads),
* - todo: read reliability, memory write, arm_flash. * memory write, arm_flash.
*/ */
/* ARM7TDMI public JTAG instructions (IR length 4). */ /* ARM7TDMI public JTAG instructions (IR length 4). */
@@ -528,10 +528,10 @@ static int execute_sys_speed(jtag_core *jc)
* Core registers r0..r14 are clobbered (acceptable for a read-then- * Core registers r0..r14 are clobbered (acceptable for a read-then-
* power-cycle flow). The core must already be halted (DBGACK). * power-cycle flow). The core must already be halted (DBGACK).
* *
* Reads real memory correctly (validated: LPC2103 vectors + multi-block * Reads real memory correctly (validated by an objcopy-verified 32 KB
* code). WORK IN PROGRESS: not yet reliable across all halt states - the * flash dump of the LPC2103). Intended flow is power-on -> one halt ->
* first read after some halts times out and leaves the core running. See * dump; see the file header and the arm7-debug-dclk-timing note for the
* the arm7-debug-dclk-timing design note. */ * repeated-halt caveat. */
int arm_debug_mem_read(jtag_core *jc, const jtag_target *t, int arm_debug_mem_read(jtag_core *jc, const jtag_target *t,
unsigned long addr, void *buf, unsigned long len) unsigned long addr, void *buf, unsigned long len)
{ {