From 44cb9dfbae562d484f1f87174550cf1e849920a7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fran=C3=A7ois?= Date: Sun, 24 May 2026 20:23:04 +0200 Subject: [PATCH] arm_debug: doc - memory read validated by 32 KB flash dump cpu_read dumped the LPC2103's full 32 KB flash to Intel HEX (objcopy-verified: all records/checksums valid, correct vectors). Update the comments to reflect the working state and the power-on -> one halt -> dump flow (context save/restore for repeated reads is the next step). Co-Authored-By: Claude Opus 4.7 --- src/modules/arm_debug/arm_debug.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/src/modules/arm_debug/arm_debug.c b/src/modules/arm_debug/arm_debug.c index 8b3f967..293498d 100644 --- a/src/modules/arm_debug/arm_debug.c +++ b/src/modules/arm_debug/arm_debug.c @@ -17,14 +17,14 @@ * use "quiet" ops that never enter Run-Test/Idle (so they don't clock * the core and clobber loaded registers), and the sys-speed poll * drives the access one clock at a time, stopping the instant - * SYSCOMP appears. Validated by reading the LPC2103 reset vectors and - * contiguous multi-block code. - * - WIP: reliability across halt states. The first read after certain - * halts can time out (sys-speed never reaches SYSCOMP), which leaves - * the core running free; subsequent reads in the same halt are - * consistent and correct. Needs a deterministic pre-read pipeline - * normalization for every halt state. See arm7-debug-dclk-timing. - * - todo: read reliability, memory write, arm_flash. + * SYSCOMP appears. Validated by dumping the LPC2103's full 32 KB + * flash to Intel HEX (objcopy-verified, correct vectors + code). + * - caveat: the read clobbers r0..r14 and there is no context + * save/restore, so the intended flow is power-on -> one halt -> dump. + * Repeated halt/read cycles without a power-cycle degrade (a later + * re-halt of the clobbered core is messy and may time out). + * - todo: context save/restore (clean resume + repeated reads), + * memory write, arm_flash. */ /* ARM7TDMI public JTAG instructions (IR length 4). */ @@ -528,10 +528,10 @@ static int execute_sys_speed(jtag_core *jc) * Core registers r0..r14 are clobbered (acceptable for a read-then- * power-cycle flow). The core must already be halted (DBGACK). * - * Reads real memory correctly (validated: LPC2103 vectors + multi-block - * code). WORK IN PROGRESS: not yet reliable across all halt states - the - * first read after some halts times out and leaves the core running. See - * the arm7-debug-dclk-timing design note. */ + * Reads real memory correctly (validated by an objcopy-verified 32 KB + * flash dump of the LPC2103). Intended flow is power-on -> one halt -> + * dump; see the file header and the arm7-debug-dclk-timing note for the + * repeated-halt caveat. */ int arm_debug_mem_read(jtag_core *jc, const jtag_target *t, unsigned long addr, void *buf, unsigned long len) {