UI restructuring:
- Dashboard (`screen_dashboard.cpp`, `screen_idx = 6`) is the new home
screen at boot. Reads Overview / Health / Analysis / Modules from
the current System every frame; per-module rows list parts grouped
by `connector_type` and a Power/Gnd inference summary (yellow when
any name-Power signal is refuted). Scrollable via PgUp/PgDn/Home/End.
Letter shortcuts: `c`=console, `s`=search, `p`=plug (alias of
connect), `t`=set-type, `e`=explore, `n`=net, `a`=analyze, `q`=quit.
- Global Ctrl-P palette (`screen_palette.cpp`) — fuzzy-finds over
registered commands + module / signal names. Activation runs the
bare command or jumps to the matching screen with state seeded.
- Unified analyze screen (`screen_analyze.cpp`, `screen_idx = 7`):
tabbed layout (`Issues / Groups / Types`), Tab or ←→ to switch
tabs, ↑/↓ to navigate the focused list. Replaces the previous
shell-bouncing `[v]erify` shortcut — `verify` content is now in
the Issues tab. Types tab attaches the decision rationale to each
signal row (fan-out / voltage / hard floor).
- Context help panel: `RenderHelpPanel(title, entries)` in
`tui_helpers.{hpp,cpp}` rendered on the right of every screen.
- Console (former "log") rename: screen 0 is `[c]onsole` in the UI
and "console" in its help-panel title. The underlying screen and
the shell prompt are unchanged.
- Esc from any non-home screen returns to the dashboard. The
dashboard itself swallows Esc; quit via `q` / the `quit` command.
`quit` now calls `screen_ptr->Exit()` directly so it works from
any screen including via the palette.
Signal type inference:
- `Signal::type` defaults to `Other` — auto-inference no longer
happens at construction.
- `infer_signal_types(System*)` is called at the end of every load.
Three rules: GndShield from name alone; Power requires name match
+ a hard fan-out floor (< 3 pins = always Other, regardless of
name or voltage) + at least one positive structural signal
(fan-out ≥ 4 OR voltage pattern in the name like `3V3`, `5V`).
- Thresholds exposed in `analysis.hpp` (`POWER_FANOUT_HARD_FLOOR`,
`POWER_FANOUT_CONFIRM_MIN`, `has_voltage_pattern`) so the analyze
screen can render the same rationale without duplicating logic.
- `set-signal-type` still wins; save/restore round-trips the type.
Analysis groups & anomalies:
- New `GroupKind::DiffBus` — ≥ 2 diff pairs sharing the same
outer-stem with consecutive integer indices are aggregated into a
single bus (`MDI[0..3]_P/N`). `MDI0` and `PCIE_TX_0` index forms
both accepted. Solo pairs under a bus-able stem fall back to
`DiffPair`.
- New `AnomalyKind::DiffBusGap` for missing lanes.
Documentation:
- `DESIGN.md`: dedicated "Categorization rules (normative)" section
consolidating signal type, NC origin, signal groups, anomalies,
component kind, and connector wiring rules with exact thresholds
and decision order.
- `doc/user/analysis.md` (new): user-facing version of the same
rules in plain language. Linked from `doc/user/index.md`.
Tests: +6 new cases (62 total). Adjusted `test_persist.cpp` to set
the signal type explicitly in the fixture (no more auto-inference).
Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
169 lines
5.2 KiB
C++
169 lines
5.2 KiB
C++
#include <doctest/doctest.h>
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#include "system/connect.hpp"
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#include "system/modules.hpp"
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#include "system/parts.hpp"
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#include "system/persist.hpp"
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#include "system/pins.hpp"
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#include "system/signals.hpp"
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#include "system/system.hpp"
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#include <filesystem>
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#include <memory>
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#include <string>
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namespace {
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std::string tmp_path(const std::string &name) {
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return (std::filesystem::temp_directory_path() / name).string();
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}
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// Build a tiny system with two modules, parts, signals, and one connection
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// with a non-trivial pin_map. Used for the round-trip test.
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std::unique_ptr<System> make_fixture() {
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auto sys = std::make_unique<System>();
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Module *bkp = sys->modules()->merge("BKP");
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Module *pl = sys->modules()->merge("PL");
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Part *p1 = new Part("U1");
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p1->connector_type = "vpx-3u-bkp-p0";
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bkp->add(p1);
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Part *p2 = new Part("J1");
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p2->connector_type = "vpx-3u-payload-p0";
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pl->add(p2);
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auto add_pin = [](Part *p, const std::string &name,
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Module *mod, const std::string &signal_name) -> Pin* {
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Pin *pin = new Pin(name);
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p->add(pin);
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if (!signal_name.empty()) {
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Signal *s = mod->signals->merge(signal_name);
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s->add(pin);
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pin->connect(s);
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}
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return pin;
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};
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Pin *a1_bkp = add_pin(p1, "A1", bkp, "GND");
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Pin *b1_bkp = add_pin(p1, "B1", bkp, "VCC");
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/*Pin *nc_bkp =*/ add_pin(p1, "C1", bkp, ""); // NC
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Pin *a1_pl = add_pin(p2, "A1", pl, "GND");
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Pin *c1_pl = add_pin(p2, "C1", pl, "VCC");
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Connection *c = new Connection("BKP/U1 <-> PL/J1", bkp, p1, pl, p2);
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c->transform_name = "vpx-3u-p0";
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c->pin_map.emplace_back(a1_bkp, a1_pl);
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c->pin_map.emplace_back(b1_bkp, c1_pl);
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sys->connections()->add(c);
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return sys;
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}
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} // namespace
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TEST_CASE("save+restore round-trip preserves modules, parts, types, signals, NC") {
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auto sys = make_fixture();
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std::string path = tmp_path("essim_roundtrip.txt");
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std::string err;
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REQUIRE(save_system(sys.get(), path, err));
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System *restored_raw = restore_system(path, err);
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REQUIRE(restored_raw != nullptr);
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std::unique_ptr<System> restored(restored_raw);
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std::filesystem::remove(path);
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CHECK(restored->modules()->size() == 2);
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Module *bkp = restored->modules()->get("BKP");
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Module *pl = restored->modules()->get("PL");
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REQUIRE(bkp); REQUIRE(pl);
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Part *p1 = bkp->get("U1");
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Part *p2 = pl->get("J1");
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REQUIRE(p1); REQUIRE(p2);
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CHECK(p1->connector_type == "vpx-3u-bkp-p0");
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CHECK(p2->connector_type == "vpx-3u-payload-p0");
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CHECK(p1->size() == 3);
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CHECK(p2->size() == 2);
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Pin *a1 = p1->get("A1");
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Pin *c1_nc = p1->get("C1");
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REQUIRE(a1); REQUIRE(c1_nc);
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REQUIRE(a1->signal());
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CHECK(a1->signal()->name == "GND");
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CHECK(c1_nc->signal() == nullptr); // NC preserved
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}
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TEST_CASE("save+restore preserves signal type overrides") {
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// The Signal ctor defaults to Other; promotion to Power/Gnd is the job
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// of `infer_signal_types(sys)` at load time. Here we just set the types
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// explicitly to assert that save/restore round-trips them.
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auto sys = make_fixture();
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Signal *vcc = sys->modules()->get("BKP")->signals->get("VCC");
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REQUIRE(vcc);
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vcc->type = SignalType::Power;
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Signal *gnd = sys->modules()->get("BKP")->signals->get("GND");
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REQUIRE(gnd);
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gnd->type = SignalType::GndShield;
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std::string path = tmp_path("essim_signal_type.txt");
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std::string err;
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REQUIRE(save_system(sys.get(), path, err));
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std::unique_ptr<System> restored(restore_system(path, err));
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REQUIRE(restored);
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std::filesystem::remove(path);
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Signal *r_vcc = restored->modules()->get("BKP")->signals->get("VCC");
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Signal *r_gnd = restored->modules()->get("BKP")->signals->get("GND");
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CHECK(r_vcc->type == SignalType::Power);
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CHECK(r_gnd->type == SignalType::GndShield);
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}
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TEST_CASE("save+restore preserves connections and pin_map") {
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auto sys = make_fixture();
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std::string path = tmp_path("essim_conn.txt");
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std::string err;
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REQUIRE(save_system(sys.get(), path, err));
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std::unique_ptr<System> restored(restore_system(path, err));
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REQUIRE(restored);
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std::filesystem::remove(path);
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CHECK(restored->connections()->size() == 1);
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Connection *c = restored->connections()->get("BKP/U1 <-> PL/J1");
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REQUIRE(c);
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CHECK(c->transform_name == "vpx-3u-p0");
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CHECK(c->pin_map.size() == 2);
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// Endpoints point into the restored system, not dangling.
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Module *bkp = restored->modules()->get("BKP");
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Module *pl = restored->modules()->get("PL");
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CHECK(c->m1 == bkp);
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CHECK(c->m2 == pl);
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CHECK(c->p1 == bkp->get("U1"));
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CHECK(c->p2 == pl->get("J1"));
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// Verify a specific wire pair.
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Pin *a1_bkp = bkp->get("U1")->get("A1");
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bool found_a1 = false;
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for (auto &wp : c->pin_map) {
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if (wp.first == a1_bkp) {
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CHECK(wp.second == pl->get("J1")->get("A1"));
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found_a1 = true;
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}
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}
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CHECK(found_a1);
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}
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TEST_CASE("restore returns nullptr on bogus path") {
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std::string err;
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System *r = restore_system("/this/path/should/not/exist", err);
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CHECK(r == nullptr);
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CHECK(!err.empty());
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}
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