Rank the spec sources (spec_source_rank: UserOverride > Bsdl > ConnectorModel > Inferred > Imported); apply_model now refuses to overwrite a spec owned by a higher-rank source, so one model never clobbers a more authoritative one. New check_source_conflicts(System*) emits SourceConflict for a pin the BSDL declares power/ground (a must-connect rail) that the netlist leaves unconnected — a rail floated in the schematic; surfaced as a sixth `verify` pass. Unit tests (75 cases) green; the real 8-card system reports 0 conflicts (its rails are all connected) while the JTAG findings remain. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
86 lines
2.8 KiB
C++
86 lines
2.8 KiB
C++
#include <doctest/doctest.h>
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#include "system/parts.hpp"
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#include "system/pin_model.hpp"
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#include "system/pin_spec.hpp"
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#include "system/pins.hpp"
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#include <string>
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#include <vector>
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namespace {
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// A stand-in PinModel: knows VCC (power) and CLK (clock input), has a 3-pin
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// canonical layout, and says nothing about anything else.
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struct FakeModel : PinModel {
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PinSpec spec_for(const std::string &name) const override {
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PinSpec s;
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if (name == "VCC") {
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s.function = PinFunction::Power;
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s.direction = PinDirection::Power;
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s.source = SpecSource::Bsdl;
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} else if (name == "CLK") {
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s.function = PinFunction::Clock;
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s.direction = PinDirection::In;
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s.source = SpecSource::Bsdl;
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}
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return s; // else default: source == None
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}
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std::vector<std::string> layout() const override {
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return {"VCC", "CLK", "GND"};
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}
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SpecSource source() const override { return SpecSource::Bsdl; }
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};
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} // namespace
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TEST_CASE("apply_model materialises layout pins and sets specs where the model speaks") {
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Part part("U1");
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part.add(new Pin("VCC")); // already present; CLK and GND are not
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FakeModel m;
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ApplyReport r = apply_model(&part, m);
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// CLK and GND materialised from layout(); VCC was already there.
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CHECK(r.materialised == 2);
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CHECK(part.exists("CLK"));
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CHECK(part.exists("GND"));
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CHECK(r.pins_total == 3);
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// Specs set only where the model speaks (VCC, CLK), not GND.
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CHECK(part.get("VCC")->spec.function == PinFunction::Power);
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CHECK(part.get("VCC")->spec.source == SpecSource::Bsdl);
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CHECK(part.get("CLK")->spec.function == PinFunction::Clock);
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CHECK(part.get("GND")->spec.source == SpecSource::None);
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CHECK(r.set == 2);
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}
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TEST_CASE("apply_model does not overwrite a spec the model is silent about") {
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Part part("U2");
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Pin *p = new Pin("DATA");
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p->spec.function = PinFunction::Signal;
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p->spec.source = SpecSource::Bsdl; // a prior model wrote this
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part.add(p);
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FakeModel m; // says nothing about DATA
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apply_model(&part, m);
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CHECK(part.get("DATA")->spec.function == PinFunction::Signal);
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CHECK(part.get("DATA")->spec.source == SpecSource::Bsdl);
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}
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TEST_CASE("apply_model never overwrites a higher-precedence source") {
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Part part("U3");
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Pin *p = new Pin("VCC");
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p->spec.function = PinFunction::Ground; // user-set, deliberately != the model
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p->spec.source = SpecSource::UserOverride;
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part.add(p);
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FakeModel m; // would set VCC = Power / Bsdl
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apply_model(&part, m);
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// UserOverride (rank 5) outranks Bsdl (rank 4): kept untouched.
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CHECK(part.get("VCC")->spec.source == SpecSource::UserOverride);
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CHECK(part.get("VCC")->spec.function == PinFunction::Ground);
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}
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