François
63ca17d048
Reorganise the tree into business vs frontend as separate directories:
src/core/{domain,imports,app} (was system/, imports/, app/)
src/frontends/tui/ (was tui/ + main.cpp)
tests/tui/ (the FTXUI-coupled helper test)
All cross-dir #include paths rewritten; same-dir includes untouched.
CMake: essim_core is the frontend-agnostic business library — links libzip,
pugixml and bsdl, NO GUI toolkit. Each frontend is a self-contained
src/frontends/<name>/ (own CMakeLists, toolkit, main.cpp) that links
essim_core, selected with -DESSIM_FRONTEND=<name> (default tui; 'none' = core +
tests only, no toolkit fetched). FTXUI moved into the tui frontend. Tests are
split: essim_tests links essim_core (no FTXUI), essim_tui_tests links essim_tui.
Verified: default tui build green (ctest 2/2); ESSIM_FRONTEND=none builds the
core + tests with FTXUI never fetched and no `essim` binary.
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
298 lines
10 KiB
C++
298 lines
10 KiB
C++
#include <doctest/doctest.h>
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#include "core/domain/analysis.hpp"
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#include "core/domain/modules.hpp"
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#include "core/domain/parts.hpp"
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#include "core/domain/pins.hpp"
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#include "core/domain/signals.hpp"
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#include "core/domain/system.hpp"
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#include <memory>
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#include <string>
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namespace {
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// Add a signal of the given name to a module, plus a single pin on a
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// helper part so the signal is not stripped by `drop_singleton_signals`
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// when callers exercise that path.
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void add_signal(Module *mod, Part *prt, const std::string &sig_name) {
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Pin *pin = new Pin("p_" + sig_name);
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prt->add(pin);
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Signal *s = mod->signals->merge(sig_name);
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s->add(pin);
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pin->connect(s);
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}
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} // namespace
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TEST_CASE("analyze detects diff pairs and reports `_P` orphans only") {
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auto sys = std::make_unique<System>();
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Module *m = sys->modules()->merge("M");
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Part *p = new Part("U1"); m->add(p);
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add_signal(m, p, "GETH_DA_P");
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add_signal(m, p, "GETH_DA_N");
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add_signal(m, p, "PCIE_RX_P"); // orphan: _P only → reported
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add_signal(m, p, "USB_DM"); // not a diff pair (no _P/_N)
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add_signal(m, p, "lower_p");
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add_signal(m, p, "lower_n"); // lowercase still matches
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add_signal(m, p, "RESET_N"); // _N only → NOT reported (active-low)
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add_signal(m, p, "BOOTMODE_N"); // _N only → NOT reported
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AnalysisReport r = analyze_system(sys.get());
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int dp = 0, orphans = 0;
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for (const auto &g : r.groups)
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if (g.kind == GroupKind::DiffPair) ++dp;
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for (const auto &a : r.anomalies)
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if (a.kind == AnomalyKind::DiffPairOrphan) ++orphans;
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CHECK(dp == 2); // GETH_DA + lower
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CHECK(orphans == 1); // only PCIE_RX_P
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}
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TEST_CASE("analyze aggregates diff pairs into a diff bus by trailing index") {
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auto sys = std::make_unique<System>();
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Module *m = sys->modules()->merge("M");
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Part *p = new Part("U1"); m->add(p);
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add_signal(m, p, "MDI0_P"); add_signal(m, p, "MDI0_N");
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add_signal(m, p, "MDI1_P"); add_signal(m, p, "MDI1_N");
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add_signal(m, p, "MDI2_P"); add_signal(m, p, "MDI2_N");
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add_signal(m, p, "MDI3_P"); add_signal(m, p, "MDI3_N");
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// Underscore-separated index variant.
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add_signal(m, p, "PCIE_TX_0_P"); add_signal(m, p, "PCIE_TX_0_N");
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add_signal(m, p, "PCIE_TX_1_P"); add_signal(m, p, "PCIE_TX_1_N");
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// A lonely pair under a bus-able stem (only one index) must stay DiffPair.
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add_signal(m, p, "USB3_TX_P"); add_signal(m, p, "USB3_TX_N");
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AnalysisReport r = analyze_system(sys.get());
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int dp = 0, db = 0;
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bool mdi_found = false, pcie_found = false;
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for (const auto &g : r.groups) {
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if (g.kind == GroupKind::DiffPair) ++dp;
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if (g.kind == GroupKind::DiffBus) ++db;
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if (g.kind == GroupKind::DiffBus && g.label.find("MDI[") == 0) {
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mdi_found = true;
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CHECK(g.lo == 0);
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CHECK(g.hi == 3);
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CHECK(g.members.size() == 8); // 4 pairs × 2 signals
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}
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if (g.kind == GroupKind::DiffBus && g.label.find("PCIE_TX_[") == 0) {
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pcie_found = true;
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CHECK(g.lo == 0);
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CHECK(g.hi == 1);
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CHECK(g.members.size() == 4);
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}
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}
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CHECK(db == 2);
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CHECK(dp == 1); // USB3_TX kept as solo DiffPair (single index — degenerate bus)
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CHECK(mdi_found);
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CHECK(pcie_found);
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}
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TEST_CASE("analyze flags a diff bus with a missing lane") {
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auto sys = std::make_unique<System>();
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Module *m = sys->modules()->merge("M");
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Part *p = new Part("U1"); m->add(p);
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add_signal(m, p, "LANE0_P"); add_signal(m, p, "LANE0_N");
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add_signal(m, p, "LANE1_P"); add_signal(m, p, "LANE1_N");
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// LANE2 missing
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add_signal(m, p, "LANE3_P"); add_signal(m, p, "LANE3_N");
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AnalysisReport r = analyze_system(sys.get());
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int gaps = 0;
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for (const auto &a : r.anomalies)
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if (a.kind == AnomalyKind::DiffBusGap) ++gaps;
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CHECK(gaps == 1);
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}
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TEST_CASE("analyze detects buses with bracketed and underscore forms") {
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auto sys = std::make_unique<System>();
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Module *m = sys->modules()->merge("M");
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Part *p = new Part("U1"); m->add(p);
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add_signal(m, p, "DATA[0]");
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add_signal(m, p, "DATA[1]");
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add_signal(m, p, "DATA[2]");
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add_signal(m, p, "ADDR_0");
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add_signal(m, p, "ADDR_1");
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add_signal(m, p, "STANDALONE");
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AnalysisReport r = analyze_system(sys.get());
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int buses = 0;
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bool data_found = false, addr_found = false;
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for (const auto &g : r.groups) {
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if (g.kind != GroupKind::Bus) continue;
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++buses;
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if (g.label.find("DATA") == 0) {
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data_found = true;
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CHECK(g.lo == 0);
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CHECK(g.hi == 2);
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CHECK(g.members.size() == 3);
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} else if (g.label.find("ADDR_") == 0) {
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addr_found = true;
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CHECK(g.lo == 0);
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CHECK(g.hi == 1);
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CHECK(g.members.size() == 2);
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}
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}
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CHECK(buses == 2);
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CHECK(data_found);
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CHECK(addr_found);
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}
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TEST_CASE("analyze flags bus gaps") {
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auto sys = std::make_unique<System>();
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Module *m = sys->modules()->merge("M");
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Part *p = new Part("U1"); m->add(p);
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add_signal(m, p, "D[0]");
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add_signal(m, p, "D[1]");
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add_signal(m, p, "D[3]"); // gap at 2
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add_signal(m, p, "D[5]"); // gap at 4
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AnalysisReport r = analyze_system(sys.get());
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int gaps = 0;
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for (const auto &a : r.anomalies)
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if (a.kind == AnomalyKind::BusGap) ++gaps;
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CHECK(gaps == 1); // one bus, one anomaly listing all missing indices
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}
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TEST_CASE("analyze ignores single-suffix \"buses\" and pure numbers") {
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auto sys = std::make_unique<System>();
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Module *m = sys->modules()->merge("M");
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Part *p = new Part("U1"); m->add(p);
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add_signal(m, p, "CLK_100MHZ"); // not a bus (single signal)
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add_signal(m, p, "GND"); // no digit suffix
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AnalysisReport r = analyze_system(sys.get());
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for (const auto &g : r.groups)
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CHECK(g.kind != GroupKind::Bus);
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}
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TEST_CASE("analyze rejects digits not preceded by `_` (false-positive guard)") {
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auto sys = std::make_unique<System>();
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Module *m = sys->modules()->merge("M");
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Part *p = new Part("U1"); m->add(p);
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// GETH_01_VDD12, GETH_01_VDD13 look like a bus with stem "GETH_01_VDD"
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// but there is no underscore before the digits — must NOT be detected.
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add_signal(m, p, "GETH_01_VDD12");
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add_signal(m, p, "GETH_01_VDD13");
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add_signal(m, p, "GETH_01_VDD14");
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AnalysisReport r = analyze_system(sys.get());
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for (const auto &g : r.groups)
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CHECK(g.kind != GroupKind::Bus);
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}
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TEST_CASE("analyze skips internal `$xxx` Mentor names") {
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auto sys = std::make_unique<System>();
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Module *m = sys->modules()->merge("M");
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Part *p = new Part("U1"); m->add(p);
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add_signal(m, p, "$N123");
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add_signal(m, p, "$N124");
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add_signal(m, p, "$N125");
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add_signal(m, p, "$SIG_P");
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add_signal(m, p, "$SIG_N");
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AnalysisReport r = analyze_system(sys.get());
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CHECK(r.groups.empty());
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CHECK(r.anomalies.empty());
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}
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TEST_CASE("analyze on empty / null system") {
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AnalysisReport r = analyze_system(nullptr);
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CHECK(r.groups.empty());
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CHECK(r.anomalies.empty());
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auto sys = std::make_unique<System>();
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r = analyze_system(sys.get());
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CHECK(r.groups.empty());
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CHECK(r.anomalies.empty());
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}
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TEST_CASE("infer_signal_types: Power requires name+structural agreement") {
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auto sys = std::make_unique<System>();
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Module *m = sys->modules()->merge("M");
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Part *p = new Part("U1"); m->add(p);
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auto fan_out = [&](Signal *s, int n) {
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for (int i = 0; i < n; ++i) {
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Pin *pin = new Pin(s->name + "_" + std::to_string(i));
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p->add(pin); s->add(pin); pin->connect(s);
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}
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};
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Signal *p_3v3 = m->signals->merge("PWR_3V3"); fan_out(p_3v3, 3); // voltage + ≥ floor → Power
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Signal *vcc = m->signals->merge("VCC"); fan_out(vcc, 5); // fan-out ≥ 4 → Power
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Signal *pwr_ok = m->signals->merge("PWR_OK"); fan_out(pwr_ok, 1); // < 3 → hard floor → Other
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Signal *pwr_2 = m->signals->merge("PWR_2"); fan_out(pwr_2, 2); // < 3 → hard floor → Other
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Signal *gnd = m->signals->merge("GND"); fan_out(gnd, 1); // gnd: name alone
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Signal *clk = m->signals->merge("CLK_50MHZ"); fan_out(clk, 3); // not power-ish → Other
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auto st = infer_signal_types(sys.get());
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CHECK(st.power == 2); // PWR_3V3, VCC
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CHECK(st.gnd == 1); // GND (name alone)
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CHECK(st.kept_other == 2); // PWR_OK, PWR_2 below the hard floor
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CHECK(p_3v3->type == SignalType::Power);
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CHECK(vcc->type == SignalType::Power);
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CHECK(gnd->type == SignalType::GndShield);
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CHECK(pwr_ok->type == SignalType::Other);
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CHECK(pwr_2->type == SignalType::Other);
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CHECK(clk->type == SignalType::Other);
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}
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TEST_CASE("infer_signal_types: fan-out hard floor overrides voltage in name") {
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auto sys = std::make_unique<System>();
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Module *m = sys->modules()->merge("M");
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Part *p = new Part("U1"); m->add(p);
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// VS_3V3 has a voltage pattern that would normally confirm Power, but
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// with only 2 pins it must still drop to Other because of the hard floor.
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Signal *s = m->signals->merge("VS_3V3");
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Pin *p1 = new Pin("p1"); p->add(p1); s->add(p1); p1->connect(s);
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Pin *p2 = new Pin("p2"); p->add(p2); s->add(p2); p2->connect(s);
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auto st = infer_signal_types(sys.get());
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CHECK(st.power == 0);
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CHECK(st.kept_other == 1);
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CHECK(s->type == SignalType::Other);
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}
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TEST_CASE("Signal ctor defaults type to Other (no auto-inference)") {
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Signal s("VCC");
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CHECK(s.type == SignalType::Other);
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}
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TEST_CASE("analyze scopes detection per module (no cross-module merge)") {
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auto sys = std::make_unique<System>();
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Module *m1 = sys->modules()->merge("M1");
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Module *m2 = sys->modules()->merge("M2");
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Part *p1 = new Part("U1"); m1->add(p1);
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Part *p2 = new Part("U1"); m2->add(p2);
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add_signal(m1, p1, "SIG_P");
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add_signal(m2, p2, "SIG_N"); // matching half lives in another module
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AnalysisReport r = analyze_system(sys.get());
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int dp = 0, orphans = 0;
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for (const auto &g : r.groups)
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if (g.kind == GroupKind::DiffPair) ++dp;
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for (const auto &a : r.anomalies)
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if (a.kind == AnomalyKind::DiffPairOrphan) ++orphans;
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CHECK(dp == 0);
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CHECK(orphans == 1); // only the `_P` side is reported (active-low rule)
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}
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