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P3.2: source precedence + model-vs-netlist conflict check

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Rank the spec sources (spec_source_rank: UserOverride > Bsdl > ConnectorModel
> Inferred > Imported); apply_model now refuses to overwrite a spec owned by a
higher-rank source, so one model never clobbers a more authoritative one. New
check_source_conflicts(System*) emits SourceConflict for a pin the BSDL
declares power/ground (a must-connect rail) that the netlist leaves
unconnected — a rail floated in the schematic; surfaced as a sixth `verify`
pass. Unit tests (75 cases) green; the real 8-card system reports 0 conflicts
(its rails are all connected) while the JTAG findings remain.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
This commit is contained in:
Foué
2026-06-03 16:08:28 +02:00
parent cb61e9b084
commit fe5b2c3d96
10 changed files with 120 additions and 8 deletions
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15
tests/test_pin_model.cpp
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@@ -68,3 +68,18 @@ TEST_CASE("apply_model does not overwrite a spec the model is silent about") {
CHECK(part.get("DATA")->spec.function == PinFunction::Signal);
CHECK(part.get("DATA")->spec.source == SpecSource::Bsdl);
}
TEST_CASE("apply_model never overwrites a higher-precedence source") {
Part part("U3");
Pin *p = new Pin("VCC");
p->spec.function = PinFunction::Ground; // user-set, deliberately != the model
p->spec.source = SpecSource::UserOverride;
part.add(p);
FakeModel m; // would set VCC = Power / Bsdl
apply_model(&part, m);
// UserOverride (rank 5) outranks Bsdl (rank 4): kept untouched.
CHECK(part.get("VCC")->spec.source == SpecSource::UserOverride);
CHECK(part.get("VCC")->spec.function == PinFunction::Ground);
}