P3.2: source precedence + model-vs-netlist conflict check
Rank the spec sources (spec_source_rank: UserOverride > Bsdl > ConnectorModel > Inferred > Imported); apply_model now refuses to overwrite a spec owned by a higher-rank source, so one model never clobbers a more authoritative one. New check_source_conflicts(System*) emits SourceConflict for a pin the BSDL declares power/ground (a must-connect rail) that the netlist leaves unconnected — a rail floated in the schematic; surfaced as a sixth `verify` pass. Unit tests (75 cases) green; the real 8-card system reports 0 conflicts (its rails are all connected) while the JTAG findings remain. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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@@ -29,6 +29,7 @@ const char *anomaly_kind_name(AnomalyKind k) {
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case AnomalyKind::JtagTapIncomplete: return "jtag-tap-incomplete";
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case AnomalyKind::JtagChainBreak: return "jtag-chain-break";
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case AnomalyKind::JtagBusUnbridged: return "jtag-bus-unbridged";
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case AnomalyKind::SourceConflict: return "source-conflict";
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}
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return "?";
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}
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@@ -37,6 +37,7 @@ enum class AnomalyKind {
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JtagTapIncomplete, ///< A TAP device is missing one of TDI/TDO/TMS/TCK.
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JtagChainBreak, ///< The TDO→TDI daisy chain is broken / not a single path.
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JtagBusUnbridged, ///< TMS or TCK is not common to all TAP devices.
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SourceConflict, ///< A model contradicts the netlist (e.g. BSDL power pin left NC).
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};
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struct Anomaly {
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@@ -1,5 +1,6 @@
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#include "bsdl_check.hpp"
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#include "connect.hpp"
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#include "modules.hpp"
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#include "nets.hpp"
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#include "parts.hpp"
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@@ -10,6 +11,7 @@
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#include <string>
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#include <unordered_map>
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#include <unordered_set>
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#include <utility>
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#include <vector>
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@@ -277,3 +279,43 @@ std::vector<Anomaly> check_jtag_chain(System *sys)
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return out;
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}
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std::vector<Anomaly> check_source_conflicts(System *sys)
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{
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std::vector<Anomaly> out;
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if (!sys)
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return out;
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// Pins bridged to a peer signal through a connection count as connected.
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std::unordered_set<Pin *> bridged;
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for (auto &ckv : *sys->connections())
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for (auto &wp : ckv.second->pin_map) {
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if (wp.first) bridged.insert(wp.first);
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if (wp.second) bridged.insert(wp.second);
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}
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for (auto &mkv : *sys->modules())
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for (auto &pkv : *mkv.second)
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for (auto &nkv : *pkv.second) {
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Pin *pin = nkv.second;
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if (pin->spec.source != SpecSource::Bsdl)
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continue;
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PinFunction f = pin->spec.function;
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if (f != PinFunction::Power && f != PinFunction::Ground)
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continue; // only must-connect rails are a clear defect
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if (pin->connected() || bridged.count(pin))
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continue;
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Anomaly a;
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a.kind = AnomalyKind::SourceConflict;
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a.module = (pin->prnt) ? pin->prnt->prnt : nullptr;
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a.message = pin_label(pin) + ": BSDL says "
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+ (f == PinFunction::Power ? "power" : "ground")
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+ " but the netlist leaves it unconnected"
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+ (pin->nc_origin == NcOrigin::ImportedUnconnected
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? " (marked NC at import)" : "");
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out.push_back(std::move(a));
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}
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return out;
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}
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@@ -25,4 +25,10 @@ std::vector<Anomaly> check_pin_specs(System *sys);
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// Empty when the system has no TAP pins.
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std::vector<Anomaly> check_jtag_chain(System *sys);
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// Conflicts between a device model and the netlist's own view of a pin. Today:
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// a pin the BSDL declares power/ground (a must-connect rail) that the netlist
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// leaves unconnected (no signal and not bridged) — i.e. a rail floated in the
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// schematic. The reverse (BSDL no-connect wired in the netlist) is `NcWired`.
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std::vector<Anomaly> check_source_conflicts(System *sys);
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#endif // _BSDL_CHECK_HPP_
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@@ -30,14 +30,17 @@ ApplyReport apply_model(Part *part, const PinModel &model)
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}
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}
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// 2. Set each pin's spec where the model speaks for it.
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// 2. Set each pin's spec where the model speaks for it — but never overwrite
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// a spec already owned by a higher-precedence source (see spec_source_rank).
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r.pins_total = (int)part->size();
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for (auto &kv : *part) {
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PinSpec s = model.spec_for(kv.first);
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if (s.source != SpecSource::None) {
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kv.second->spec = s;
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++r.set;
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}
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if (s.source == SpecSource::None)
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continue;
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if (spec_source_rank(s.source) < spec_source_rank(kv.second->spec.source))
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continue;
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kv.second->spec = s;
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++r.set;
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}
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return r;
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}
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@@ -51,4 +51,21 @@ inline PinFunction function_from_signal_type(SignalType t)
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}
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}
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// Precedence of spec sources: a higher rank wins when two sources speak for the
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// same pin. A user override beats any model; a device model (BSDL) beats a
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// connector layout; both beat plain import / inference. Used by apply_model to
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// avoid clobbering a more authoritative spec.
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inline int spec_source_rank(SpecSource s)
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{
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switch (s) {
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case SpecSource::None: return 0;
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case SpecSource::Imported: return 1;
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case SpecSource::Inferred: return 2;
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case SpecSource::ConnectorModel: return 3;
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case SpecSource::Bsdl: return 4;
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case SpecSource::UserOverride: return 5;
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}
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return 0;
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}
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#endif // _PIN_SPEC_HPP_
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@@ -312,6 +312,13 @@ void Tui::RegisterCommands() {
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Print(" [" + std::string(anomaly_kind_name(a.kind)) + "] " + a.message);
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Print("verify: " + std::to_string(jtag_anoms.size())
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+ " JTAG chain anomaly(ies).");
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// Model-vs-netlist conflicts (e.g. a BSDL power pin left unconnected).
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auto conflict_anoms = check_source_conflicts(sys.get());
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for (const auto &a : conflict_anoms)
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Print(" [" + std::string(anomaly_kind_name(a.kind)) + "] " + a.message);
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Print("verify: " + std::to_string(conflict_anoms.size())
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+ " source-conflict(s).");
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}, true,
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"check pin roles, bridged-net consistency, and model-driven pin specs (contention/undriven/NC)" };
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