P3: BSDL completeness check (missing device power/ground pins)

check_bsdl_completeness(System*): for each BSDL-attached part, re-parse the
.bsd and report the device power/ground ports with no matching pin on the
netlist part (matched by port name or physical pad) — a rail the schematic
symbol is missing. One aggregated BsdlPinMissing per part; restricted to
power/ground so unused I/O balls don't create noise. Surfaced as a 7th verify
pass and in the analyze/dashboard model counts. 76 cases / 327 assertions
green; the real 8-card system reports 0 (all FPGA rails present). This closes
out P3.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>

tests/test_bsdl_apply.cpp

@@ -1,5 +1,7 @@
 #include <doctest/doctest.h>
 
+#include "system/analysis.hpp"
+#include "system/bsdl_check.hpp"
 #include "system/bsdl_model.hpp"
 #include "system/parts.hpp"
 #include "system/pins.hpp"
@@ -141,3 +143,27 @@ TEST_CASE("attached BSDL path persists and re-applies on restore") {
     std::remove(bsd);
     std::remove(snap);
 }
+
+TEST_CASE("check_bsdl_completeness flags a device power pin absent from the part") {
+    const char *bsd = "test_complete_demo.bsd";
+    { std::ofstream o(bsd); o << DEMO_BSDL; }
+
+    System sys;
+    Module *m = sys.modules()->merge("CARD");
+    Part *u = new Part("U1");
+    // All pins EXCEPT VDD (a power port at ball C1) → its port is unmatched.
+    for (const char *n : {"TCK", "TDI", "TDO", "TMS", "IO1", "GND"})
+        u->add(new Pin(n));
+    u->bsdl_path = bsd;
+    m->add(u);
+
+    auto a = check_bsdl_completeness(&sys);
+    REQUIRE(a.size() == 1);
+    CHECK(a[0].kind == AnomalyKind::BsdlPinMissing);
+
+    // With VDD present (by ball or by name), no completeness issue.
+    u->add(new Pin("VDD"));
+    CHECK(check_bsdl_completeness(&sys).empty());
+
+    std::remove(bsd);
+}