P3: BSDL completeness check (missing device power/ground pins)

check_bsdl_completeness(System*): for each BSDL-attached part, re-parse the
.bsd and report the device power/ground ports with no matching pin on the
netlist part (matched by port name or physical pad) — a rail the schematic
symbol is missing. One aggregated BsdlPinMissing per part; restricted to
power/ground so unused I/O balls don't create noise. Surfaced as a 7th verify
pass and in the analyze/dashboard model counts. 76 cases / 327 assertions
green; the real 8-card system reports 0 (all FPGA rails present). This closes
out P3.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>

src/tui/screen_dashboard.cpp

@@ -154,7 +154,8 @@ Component Tui::BuildDashboardScreen() {
       // reusing the nets computed above.
       int n_model = (int)(check_pin_specs(sys.get(), &nets).size()
                           + check_jtag_chain(sys.get(), &nets).size()
-                          + check_source_conflicts(sys.get()).size());
+                          + check_source_conflicts(sys.get()).size()
+                          + check_bsdl_completeness(sys.get()).size());
       health_rows.push_back(health_line(n_model == 0,
           "model:   " + std::to_string(n_model) + " BSDL/JTAG anomaly(ies)"));