Signal types, pin role expectations, and a doctest suite.

Domain
- Signal carries a SignalType (Power/GndShield/Other), auto-inferred
  from the name in Signal::Signal via infer_signal_type. Override with
  the new `set-signal-type` command.
- SignalType extracted to its own header so Pin can store an
  `expected_signal_type` without a pins↔signals include cycle.
- pin_role(connector_type, pin_name) → SignalType lookup, called from
  set-type to populate each Pin's expected_signal_type. The VPX 3U
  table is currently a stub (returns Other).
- New `verify` command walks typed parts and reports pins whose
  connected signal's type doesn't match the expectation.
- ODS importer no longer drops pins with empty signal column — they
  stay in the part as NC, matching the rule "a pin is either NC or
  connected to a signal".
- persist: new S tag for non-default signal type overrides.

Tests
- doctest v2.4.11 via FetchContent (with CMAKE_POLICY_VERSION_MINIMUM
  shim, doctest's CMakeLists has a too-old floor for current CMake).
- Source files moved into a static library `essim_lib` so both `essim`
  and `essim_tests` reuse the same compilation. main.cpp is the only
  file kept out of the lib.
- Layer 1 (pure helpers): ToLower, LongestCommonPrefix, Tokenize,
  NaturalLess (numeric/case/leading-zero edge cases + total-order
  invariants), signal_type round-trips and infer_signal_type families,
  VpxTransform registry + symmetry + reference-table mapping for
  connector P0 row 1, IdentityTransform same-name wiring.
- Layer 2 (round-trip): build a synthetic 2-module system in code,
  save → restore → assert modules / parts / connector_types / NC pins
  / signal type overrides / connections + pin_map are all preserved.
- Tui::Tokenize moved to a free function in tui_helpers so tests can
  call it without dragging ftxui into the unit-test layer.
- 27 test cases, 123 assertions, ~150 ms.

Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>

tests/doctest_main.cpp

@@ -0,0 +1,2 @@
+#define DOCTEST_CONFIG_IMPLEMENT_WITH_MAIN
+#include <doctest/doctest.h>

tests/test_helpers.cpp

@@ -0,0 +1,71 @@
+#include <doctest/doctest.h>
+
+#include "tui/tui_helpers.hpp"
+
+#include <algorithm>
+#include <vector>
+
+TEST_CASE("ToLower") {
+    CHECK(ToLower("ABC") == "abc");
+    CHECK(ToLower("aBc 123") == "abc 123");
+    CHECK(ToLower("") == "");
+}
+
+TEST_CASE("LongestCommonPrefix") {
+    CHECK(LongestCommonPrefix({}) == "");
+    CHECK(LongestCommonPrefix({"foo"}) == "foo");
+    CHECK(LongestCommonPrefix({"foo", "foobar", "foobaz"}) == "foo");
+    CHECK(LongestCommonPrefix({"abc", "xyz"}) == "");
+    CHECK(LongestCommonPrefix({"abc", "abc"}) == "abc");
+}
+
+TEST_CASE("Tokenize splits on whitespace") {
+    CHECK(Tokenize("").empty());
+    CHECK(Tokenize("   ").empty());
+    auto t = Tokenize("a b  c");
+    CHECK(t == std::vector<std::string>{"a", "b", "c"});
+}
+
+TEST_CASE("Tokenize preserves quoted spaces") {
+    auto t = Tokenize("load \"my mod\" /tmp/x mentor");
+    CHECK(t == std::vector<std::string>{"load", "my mod", "/tmp/x", "mentor"});
+}
+
+TEST_CASE("Tokenize handles tabs as separators") {
+    auto t = Tokenize("a\tb\tc");
+    CHECK(t == std::vector<std::string>{"a", "b", "c"});
+}
+
+TEST_CASE("NaturalLess: numeric runs sort numerically") {
+    CHECK(NaturalLess("J1", "J2"));
+    CHECK(NaturalLess("J2", "J10"));
+    CHECK(NaturalLess("J9", "J10"));
+    CHECK(!NaturalLess("J10", "J2"));
+    CHECK(!NaturalLess("J10", "J10"));
+}
+
+TEST_CASE("NaturalLess: case insensitive for letters") {
+    CHECK(NaturalLess("abc", "ABD"));
+    CHECK(!NaturalLess("ABD", "abc"));
+    CHECK(!NaturalLess("abc", "ABC"));
+}
+
+TEST_CASE("NaturalLess: leading zeros tie-break") {
+    CHECK(NaturalLess("J01", "J1"));
+    CHECK(!NaturalLess("J1", "J01"));
+}
+
+TEST_CASE("NaturalLess: produces a sorted order over a connector-style list") {
+    std::vector<std::string> v = {"J22", "J1", "J10", "J2", "P100", "P21", "P2"};
+    std::sort(v.begin(), v.end(), NaturalLess);
+    CHECK(v == std::vector<std::string>{"J1", "J2", "J10", "J22", "P2", "P21", "P100"});
+}
+
+TEST_CASE("NaturalLess: total order axioms") {
+    // !(a < a)
+    CHECK(!NaturalLess("foo", "foo"));
+    CHECK(!NaturalLess("J10", "J10"));
+    // a < b ⇒ !(b < a)
+    CHECK(NaturalLess("J1", "J2"));
+    CHECK(!NaturalLess("J2", "J1"));
+}

tests/test_persist.cpp

@@ -0,0 +1,166 @@
+#include <doctest/doctest.h>
+
+#include "system/connect.hpp"
+#include "system/modules.hpp"
+#include "system/parts.hpp"
+#include "system/persist.hpp"
+#include "system/pins.hpp"
+#include "system/signals.hpp"
+#include "system/system.hpp"
+
+#include <filesystem>
+#include <memory>
+#include <string>
+
+namespace {
+
+std::string tmp_path(const std::string &name) {
+    return (std::filesystem::temp_directory_path() / name).string();
+}
+
+// Build a tiny system with two modules, parts, signals, and one connection
+// with a non-trivial pin_map. Used for the round-trip test.
+std::unique_ptr<System> make_fixture() {
+    auto sys = std::make_unique<System>();
+    Module *bkp = sys->modules()->merge("BKP");
+    Module *pl  = sys->modules()->merge("PL");
+
+    Part *p1 = new Part("U1");
+    p1->connector_type = "vpx-3u-bkp-p0";
+    bkp->add(p1);
+    Part *p2 = new Part("J1");
+    p2->connector_type = "vpx-3u-payload-p0";
+    pl->add(p2);
+
+    auto add_pin = [](Part *p, const std::string &name,
+                      Module *mod, const std::string &signal_name) -> Pin* {
+        Pin *pin = new Pin(name);
+        p->add(pin);
+        if (!signal_name.empty()) {
+            Signal *s = mod->signals->merge(signal_name);
+            s->add(pin);
+            pin->connect(s);
+        }
+        return pin;
+    };
+
+    Pin *a1_bkp = add_pin(p1, "A1", bkp, "GND");
+    Pin *b1_bkp = add_pin(p1, "B1", bkp, "VCC");
+    /*Pin *nc_bkp =*/ add_pin(p1, "C1", bkp, "");  // NC
+
+    Pin *a1_pl  = add_pin(p2, "A1", pl,  "GND");
+    Pin *c1_pl  = add_pin(p2, "C1", pl,  "VCC");
+
+    Connection *c = new Connection("BKP/U1 <-> PL/J1", bkp, p1, pl, p2);
+    c->transform_name = "vpx-3u-p0";
+    c->pin_map.emplace_back(a1_bkp, a1_pl);
+    c->pin_map.emplace_back(b1_bkp, c1_pl);
+    sys->connections()->add(c);
+
+    return sys;
+}
+
+}  // namespace
+
+TEST_CASE("save+restore round-trip preserves modules, parts, types, signals, NC") {
+    auto sys = make_fixture();
+    std::string path = tmp_path("essim_roundtrip.txt");
+
+    std::string err;
+    REQUIRE(save_system(sys.get(), path, err));
+
+    System *restored_raw = restore_system(path, err);
+    REQUIRE(restored_raw != nullptr);
+    std::unique_ptr<System> restored(restored_raw);
+    std::filesystem::remove(path);
+
+    CHECK(restored->modules()->size() == 2);
+
+    Module *bkp = restored->modules()->get("BKP");
+    Module *pl  = restored->modules()->get("PL");
+    REQUIRE(bkp); REQUIRE(pl);
+
+    Part *p1 = bkp->get("U1");
+    Part *p2 = pl->get("J1");
+    REQUIRE(p1); REQUIRE(p2);
+    CHECK(p1->connector_type == "vpx-3u-bkp-p0");
+    CHECK(p2->connector_type == "vpx-3u-payload-p0");
+
+    CHECK(p1->size() == 3);
+    CHECK(p2->size() == 2);
+
+    Pin *a1 = p1->get("A1");
+    Pin *c1_nc = p1->get("C1");
+    REQUIRE(a1); REQUIRE(c1_nc);
+    REQUIRE(a1->signal());
+    CHECK(a1->signal()->name == "GND");
+    CHECK(c1_nc->signal() == nullptr);  // NC preserved
+}
+
+TEST_CASE("save+restore preserves signal type overrides") {
+    auto sys = make_fixture();
+    // Force a non-default override on a signal that auto-infers as Other.
+    Signal *vcc = sys->modules()->get("BKP")->signals->get("VCC");
+    REQUIRE(vcc);
+    CHECK(vcc->type == SignalType::Power);  // auto-detected from "VCC"
+
+    Signal *gnd = sys->modules()->get("BKP")->signals->get("GND");
+    REQUIRE(gnd);
+    CHECK(gnd->type == SignalType::GndShield);
+
+    std::string path = tmp_path("essim_signal_type.txt");
+    std::string err;
+    REQUIRE(save_system(sys.get(), path, err));
+
+    std::unique_ptr<System> restored(restore_system(path, err));
+    REQUIRE(restored);
+    std::filesystem::remove(path);
+
+    Signal *r_vcc = restored->modules()->get("BKP")->signals->get("VCC");
+    Signal *r_gnd = restored->modules()->get("BKP")->signals->get("GND");
+    CHECK(r_vcc->type == SignalType::Power);
+    CHECK(r_gnd->type == SignalType::GndShield);
+}
+
+TEST_CASE("save+restore preserves connections and pin_map") {
+    auto sys = make_fixture();
+    std::string path = tmp_path("essim_conn.txt");
+    std::string err;
+    REQUIRE(save_system(sys.get(), path, err));
+
+    std::unique_ptr<System> restored(restore_system(path, err));
+    REQUIRE(restored);
+    std::filesystem::remove(path);
+
+    CHECK(restored->connections()->size() == 1);
+    Connection *c = restored->connections()->get("BKP/U1 <-> PL/J1");
+    REQUIRE(c);
+    CHECK(c->transform_name == "vpx-3u-p0");
+    CHECK(c->pin_map.size() == 2);
+
+    // Endpoints point into the restored system, not dangling.
+    Module *bkp = restored->modules()->get("BKP");
+    Module *pl  = restored->modules()->get("PL");
+    CHECK(c->m1 == bkp);
+    CHECK(c->m2 == pl);
+    CHECK(c->p1 == bkp->get("U1"));
+    CHECK(c->p2 == pl->get("J1"));
+
+    // Verify a specific wire pair.
+    Pin *a1_bkp = bkp->get("U1")->get("A1");
+    bool found_a1 = false;
+    for (auto &wp : c->pin_map) {
+        if (wp.first == a1_bkp) {
+            CHECK(wp.second == pl->get("J1")->get("A1"));
+            found_a1 = true;
+        }
+    }
+    CHECK(found_a1);
+}
+
+TEST_CASE("restore returns nullptr on bogus path") {
+    std::string err;
+    System *r = restore_system("/this/path/should/not/exist", err);
+    CHECK(r == nullptr);
+    CHECK(!err.empty());
+}

tests/test_signal_type.cpp

@@ -0,0 +1,68 @@
+#include <doctest/doctest.h>
+
+#include "system/signal_type.hpp"
+
+TEST_CASE("signal_type_name round-trips with from_name") {
+    SignalType t;
+    REQUIRE(signal_type_from_name("power", t));
+    CHECK(t == SignalType::Power);
+    REQUIRE(signal_type_from_name("gnd", t));
+    CHECK(t == SignalType::GndShield);
+    REQUIRE(signal_type_from_name("other", t));
+    CHECK(t == SignalType::Other);
+
+    CHECK(std::string(signal_type_name(SignalType::Power)) == "power");
+    CHECK(std::string(signal_type_name(SignalType::GndShield)) == "gnd");
+    CHECK(std::string(signal_type_name(SignalType::Other)) == "other");
+}
+
+TEST_CASE("signal_type_from_name accepts aliases and is case-insensitive") {
+    SignalType t;
+    REQUIRE(signal_type_from_name("Power", t));   CHECK(t == SignalType::Power);
+    REQUIRE(signal_type_from_name("GROUND", t));  CHECK(t == SignalType::GndShield);
+    REQUIRE(signal_type_from_name("shield", t));  CHECK(t == SignalType::GndShield);
+    REQUIRE(signal_type_from_name("g", t));       CHECK(t == SignalType::GndShield);
+    REQUIRE(signal_type_from_name("p", t));       CHECK(t == SignalType::Power);
+    REQUIRE(signal_type_from_name("o", t));       CHECK(t == SignalType::Other);
+}
+
+TEST_CASE("signal_type_from_name rejects garbage") {
+    SignalType t;
+    CHECK(!signal_type_from_name("", t));
+    CHECK(!signal_type_from_name("foobar", t));
+    CHECK(!signal_type_from_name("pow", t));
+}
+
+TEST_CASE("infer_signal_type: GND family") {
+    CHECK(infer_signal_type("GND")        == SignalType::GndShield);
+    CHECK(infer_signal_type("GROUND")     == SignalType::GndShield);
+    CHECK(infer_signal_type("GND_RET")    == SignalType::GndShield);
+    CHECK(infer_signal_type("GNDA")       == SignalType::GndShield);
+    CHECK(infer_signal_type("CHASSIS_GND")== SignalType::GndShield);
+    CHECK(infer_signal_type("SHIELD")     == SignalType::GndShield);
+    CHECK(infer_signal_type("EARTH")      == SignalType::GndShield);
+}
+
+TEST_CASE("infer_signal_type: power family") {
+    CHECK(infer_signal_type("VCC")           == SignalType::Power);
+    CHECK(infer_signal_type("VDD_3V3")       == SignalType::Power);
+    CHECK(infer_signal_type("PWR_VS3_5V0")   == SignalType::Power);
+    CHECK(infer_signal_type("POWER_VBAT")    == SignalType::Power);
+    CHECK(infer_signal_type("VS3_5V0")       == SignalType::Power);
+    CHECK(infer_signal_type("+5V")           == SignalType::Power);
+    CHECK(infer_signal_type("-12V")          == SignalType::Power);
+    CHECK(infer_signal_type("VBAT_SENSE")    == SignalType::Power);
+}
+
+TEST_CASE("infer_signal_type: other (data signals)") {
+    CHECK(infer_signal_type("CLK_50MHZ")          == SignalType::Other);
+    CHECK(infer_signal_type("JTAG_TCK")           == SignalType::Other);
+    CHECK(infer_signal_type("BPB_TO_SSU_RESET")   == SignalType::Other);
+    CHECK(infer_signal_type("TEMP_01_RET")        == SignalType::Other);
+}
+
+TEST_CASE("infer_signal_type: empty / weird names default to Other") {
+    CHECK(infer_signal_type("")    == SignalType::Other);
+    CHECK(infer_signal_type("NC")  == SignalType::Other);
+    CHECK(infer_signal_type("???") == SignalType::Other);
+}

tests/test_vpx_transform.cpp

@@ -0,0 +1,124 @@
+#include <doctest/doctest.h>
+
+#include "system/modules.hpp"
+#include "system/parts.hpp"
+#include "system/pins.hpp"
+#include "system/signals.hpp"
+#include "system/system.hpp"
+#include "system/transform.hpp"
+#include "system/transform_vpx.hpp"
+
+#include <map>
+#include <memory>
+#include <set>
+#include <string>
+
+namespace {
+
+// Build a Part with `pin_names` pins, attached to a fresh module so prnt
+// chains exist (set-type's validation depends on pins; transforms don't).
+Part *make_part(Module *mod, const std::string &part_name,
+                const std::vector<std::string> &pin_names) {
+    Part *p = new Part(part_name);
+    mod->add(p);  // sets p->prnt = mod
+    for (const auto &n : pin_names) {
+        Pin *pin = new Pin(n);
+        p->add(pin);
+    }
+    return p;
+}
+
+// VPX 3U bkp pinout for connector P0: 9 cols A-I × 1 row of "1".
+std::vector<std::string> bkp_p0_pins_row1() {
+    std::vector<std::string> out;
+    for (char c = 'A'; c <= 'I'; ++c) out.push_back(std::string(1, c) + "1");
+    return out;
+}
+std::vector<std::string> payload_p0_pins_row1() {
+    std::vector<std::string> out;
+    for (char c = 'A'; c <= 'G'; ++c) out.push_back(std::string(1, c) + "1");
+    return out;
+}
+
+}  // namespace
+
+TEST_CASE("VPX transform registered and looked up by name") {
+    auto &reg = TransformRegistry::get();
+    Transform *t = reg.lookup("vpx-3u-bkp-p0", "vpx-3u-payload-p0");
+    REQUIRE(t != reg.identity());
+    CHECK(t->name == "vpx-3u-p0");
+}
+
+TEST_CASE("VPX transform lookup is symmetric (both pair orders work)") {
+    auto &reg = TransformRegistry::get();
+    Transform *forward  = reg.lookup("vpx-3u-bkp-p1", "vpx-3u-payload-p1");
+    Transform *backward = reg.lookup("vpx-3u-payload-p1", "vpx-3u-bkp-p1");
+    REQUIRE(forward != reg.identity());
+    CHECK(forward == backward);
+}
+
+TEST_CASE("VPX transform refuses non-matching pairs (returns identity)") {
+    auto &reg = TransformRegistry::get();
+    CHECK(reg.lookup("vpx-3u-bkp-p0", "vpx-3u-payload-p1") == reg.identity());
+    CHECK(reg.lookup("vpx-3u-bkp-p0", "vpx-3u-bkp-p0") == reg.identity());
+    CHECK(reg.lookup("foo", "bar") == reg.identity());
+}
+
+TEST_CASE("VPX P0 row 1 mapping matches the reference table") {
+    // bkp_to_payload PCORR[0] row 1: A→A, B→C, C→C, D→C, E→D, F→E, G→E, H→F, I→G.
+    Module mod("M");
+    Part *bkp = make_part(&mod, "BKP", bkp_p0_pins_row1());
+    Part *pl  = make_part(&mod, "PL",  payload_p0_pins_row1());
+    bkp->connector_type = "vpx-3u-bkp-p0";
+    pl->connector_type  = "vpx-3u-payload-p0";
+
+    auto &reg = TransformRegistry::get();
+    Transform *t = reg.lookup(bkp->connector_type, pl->connector_type);
+    REQUIRE(t != reg.identity());
+
+    auto pin_map = t->apply(bkp, pl);
+
+    // Build (bkp_pin_name → payload_pin_name) map for easy assertion.
+    std::map<std::string, std::string> got;
+    for (auto &wp : pin_map) got[wp.first->name] = wp.second->name;
+
+    std::map<std::string, std::string> expected = {
+        {"A1","A1"}, {"B1","C1"}, {"C1","C1"}, {"D1","C1"},
+        {"E1","D1"}, {"F1","E1"}, {"G1","E1"}, {"H1","F1"},
+        {"I1","G1"},
+    };
+    CHECK(got == expected);
+}
+
+TEST_CASE("VPX transform skips pins missing on the target side") {
+    // bkp has all 9 cols; payload has only A1, B1 → most bkp pins should drop.
+    Module mod("M");
+    Part *bkp = make_part(&mod, "BKP", bkp_p0_pins_row1());
+    Part *pl  = make_part(&mod, "PL",  {"A1", "B1"});
+    bkp->connector_type = "vpx-3u-bkp-p0";
+    pl->connector_type  = "vpx-3u-payload-p0";
+
+    auto &reg = TransformRegistry::get();
+    Transform *t = reg.lookup(bkp->connector_type, pl->connector_type);
+    auto pin_map = t->apply(bkp, pl);
+
+    std::set<std::string> bkp_used;
+    for (auto &wp : pin_map) bkp_used.insert(wp.first->name);
+    // A1 maps to A1 (present), B1→C1 (absent), C1→C1 (absent), D1→C1 (absent),
+    // E1→D1 (absent), …, the only target-pin that exists for the row 1 mapping
+    // besides A1 is none — so only A1 keeps its wire (B1 in payload isn't
+    // a target of any bkp col on row 1).
+    CHECK(bkp_used == std::set<std::string>{"A1"});
+}
+
+TEST_CASE("Identity fallback wires same-named pins") {
+    Module mod("M");
+    Part *a = make_part(&mod, "A", {"X1", "X2", "Y1"});
+    Part *b = make_part(&mod, "B", {"X1", "X2", "Z1"});
+    auto &reg = TransformRegistry::get();
+    auto pin_map = reg.identity()->apply(a, b);
+
+    std::set<std::string> wired;
+    for (auto &wp : pin_map) wired.insert(wp.first->name);
+    CHECK(wired == std::set<std::string>{"X1", "X2"});
+}