183 lines
5.8 KiB
Plaintext
183 lines
5.8 KiB
Plaintext
#
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# lib jtag core init config script
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#
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# This script is built-in the jtag library and is executed at startup to apply
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# the default variables values.
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#
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# You can put a "config.script" file in the JTAG boundaryscanner software's
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# folder to change one or more of these variables if needed.
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# Your "config.script" will be executed right after this script at startup.
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# The syntax to use in your script is exactly the same.
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#
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# ----------------------------------------------------------------------------
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# ----------------------------------------------------------------------------
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# Log messages filter level
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#
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# 0 : Debug messages
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# 1 : Info level 0 messages
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# 2 : Info level 1 messages
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# 3 : Warning level messages
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# 4 : Error level messages
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# 5 : No log / no message
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set LOG_MESSAGES_FILTER_LEVEL 1
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# Log file
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#set LOG_MESSAGES_FILE_OUTPUT "logs_file.txt"
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# ----------------------------------------------------------------------------
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# ----------------------------------------------------------------------------
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#
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# Pins name sorter
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#
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# 0 To keep the bsdl pins order.
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# 1 To sort the bsdl pins name.
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#
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set BSDL_LOADER_SORT_PINS_NAME 1
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# ----------------------------------------------------------------------------
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# ----------------------------------------------------------------------------
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#
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# This section expose the FTDI probes parameters
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#
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#
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# Parameters to compute the FDTI FT2232D/H clock divisor.
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# ( TCK clock = (12Mhz or 60Mhz)/ ((1 + ([ValueH << 8 | ValueL]))*2) )
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#
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# Internal clock : FT2232H -> 60 MHz, FT2232D -> 12MHz
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set PROBE_FTDI_INTERNAL_FREQ_KHZ 60000
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# Max TCK Clock
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set PROBE_FTDI_TCK_FREQ_KHZ 1000
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#
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# To enable the RTCK / adaptative clock mode set the following
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# variable to 1.
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# Warning : Need a FDTI chip supporting this mode (FT2232H,...)
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#
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set PROBE_FTDI_JTAG_ENABLE_RTCK 0
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#
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# Probe internal mapping
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#
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# Olimex ARM-USB-OCD-H JTAG signals example
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#
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# VREF – voltage follower input for the output buffers adjust
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# JTAG signals as per your target board voltage levels
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#
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# The TCK/TDI/TDO/TMS signals are fixed to these pins
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# ADBUS0 -> TCK; (out)
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# ADBUS1 -> TDI; (out)
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# ADBUS2 -> TDO; (in)
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# ADBUS3 -> TMS; (out)
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# ADBUS4 -> 0 to enable JTAG buffers; (GPIOL0) (out)
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# ADBUS5 -> 0 if target present; (GPIOL1) (in)
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# ADBUS6 -> TSRST in; (GPIOL2) (in)
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# ADBUS7 -> RTCK; (in) (GPIOL3) (in)
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# ACBUS0 -> TRST; (GPIOH0)
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# ACBUS1 -> SRST; (GPIOH1)
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# ACBUS2 -> TRST buffer enable (GPIOH2)
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# ACBUS3 -> RED LED; (GPIOH3)
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#
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# Set the internal GPIO direction (0 -> input, 1 -> output)
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#
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set PROBE_FTDI_SET_PIN_DIR_ADBUS0 1 # TCK -> out
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set PROBE_FTDI_SET_PIN_DIR_ADBUS1 1 # TDI -> out
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set PROBE_FTDI_SET_PIN_DIR_ADBUS2 0 # TDO -> in
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set PROBE_FTDI_SET_PIN_DIR_ADBUS3 1 # TMS -> out
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set PROBE_FTDI_SET_PIN_DIR_ADBUS4 1 # Buffers enable -> out
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set PROBE_FTDI_SET_PIN_DIR_ADBUS5 0 # Target presence : 0 if target present -> in
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set PROBE_FTDI_SET_PIN_DIR_ADBUS6 0 # TSRST -> in
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set PROBE_FTDI_SET_PIN_DIR_ADBUS7 0 # RTCK -> in
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set PROBE_FTDI_SET_PIN_DIR_ACBUS0 1 # TRST -> out
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set PROBE_FTDI_SET_PIN_DIR_ACBUS1 1 # SRST -> out
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set PROBE_FTDI_SET_PIN_DIR_ACBUS2 1 # TRST buffer enable -> out
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set PROBE_FTDI_SET_PIN_DIR_ACBUS3 1 # RED LED -> out
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#
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# Set the internal GPIOs output state
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#
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set PROBE_FTDI_SET_PIN_DEFAULT_STATE_ADBUS0 0
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set PROBE_FTDI_SET_PIN_DEFAULT_STATE_ADBUS1 0
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set PROBE_FTDI_SET_PIN_DEFAULT_STATE_ADBUS2 0
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set PROBE_FTDI_SET_PIN_DEFAULT_STATE_ADBUS3 1
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set PROBE_FTDI_SET_PIN_DEFAULT_STATE_ADBUS4 0 # JTAG buffer enable (active low)
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set PROBE_FTDI_SET_PIN_DEFAULT_STATE_ADBUS5 0
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set PROBE_FTDI_SET_PIN_DEFAULT_STATE_ADBUS6 0
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set PROBE_FTDI_SET_PIN_DEFAULT_STATE_ADBUS7 0
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set PROBE_FTDI_SET_PIN_DEFAULT_STATE_ACBUS0 0 # TRST
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set PROBE_FTDI_SET_PIN_DEFAULT_STATE_ACBUS1 0 # SRST
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set PROBE_FTDI_SET_PIN_DEFAULT_STATE_ACBUS2 0 # TRST buffer enable
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set PROBE_FTDI_SET_PIN_DEFAULT_STATE_ACBUS3 0 # RED LED
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#
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# Set the internal GPIOs polarity
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# 0 : Active High.
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# 1 : Active Low.
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#
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set PROBE_FTDI_SET_PIN_POLARITY_ADBUS0 0
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set PROBE_FTDI_SET_PIN_POLARITY_ADBUS1 0
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set PROBE_FTDI_SET_PIN_POLARITY_ADBUS2 0
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set PROBE_FTDI_SET_PIN_POLARITY_ADBUS3 0
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set PROBE_FTDI_SET_PIN_POLARITY_ADBUS4 0
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set PROBE_FTDI_SET_PIN_POLARITY_ADBUS5 0
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set PROBE_FTDI_SET_PIN_POLARITY_ADBUS6 0
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set PROBE_FTDI_SET_PIN_POLARITY_ADBUS7 0
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set PROBE_FTDI_SET_PIN_POLARITY_ACBUS0 1 # TRST is active-low
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set PROBE_FTDI_SET_PIN_POLARITY_ACBUS1 0
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set PROBE_FTDI_SET_PIN_POLARITY_ACBUS2 0
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set PROBE_FTDI_SET_PIN_POLARITY_ACBUS3 0
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#
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# Assign the TRST / SRST control pins
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# 0<>7 : ADBUS
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# 8<>11 : ACBUS
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# Set to -1 when not available/used.
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#
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set PROBE_FTDI_SET_TRST_OE_PINNUM 10
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set PROBE_FTDI_SET_TRST_STATE_PINNUM 8
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set PROBE_FTDI_SET_SRST_OE_PINNUM -1
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set PROBE_FTDI_SET_SRST_STATE_PINNUM -1
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set PROBE_FTDI_SET_CONNECTION_LED_PINNUM 11
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set PROBE_FTDI_JTAG_TRST_DELAY_MS 200
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# ----------------------------------------------------------------------------
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# ----------------------------------------------------------------------------
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set PROBE_LINUXGPIO_ENABLE 0
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set PROBE_LINUXGPIO_BASE_FOLDER "/sys/class/gpio"
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set PROBE_LINUXGPIO_TMS_PIN 24
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set PROBE_LINUXGPIO_TDI_PIN 25
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set PROBE_LINUXGPIO_TDO_PIN 26
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set PROBE_LINUXGPIO_TCK_PIN 27
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set PROBE_LINUXGPIO_TMS_PIN_INVERT_POLARITY 0
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set PROBE_LINUXGPIO_TDI_PIN_INVERT_POLARITY 0
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set PROBE_LINUXGPIO_TDO_PIN_INVERT_POLARITY 0
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set PROBE_LINUXGPIO_TCK_PIN_INVERT_POLARITY 0
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