Make the system-speed memory read reliable within a halt:
- debug entry mirrors OpenOCD's arm7_9_debug_entry: change_to_arm when
the core halted in Thumb, then read all 16 core registers. That fixed
STMIA+NOP+NOP+16 sequence flushes the firmware out of the pipeline and
leaves a deterministic state for both Thumb and ARM halts.
- warm-up read: the first system-speed read after debug entry normalizes
the sys-speed pipeline but its own result is unreliable, so do one
throwaway read block and discard it. Every read after it is consistent
and correct (analogous to the FTDI stale-first-read).
Within one clean halt, reads now come back correct (no misalignment).
Repeated halt/read cycles without a power-cycle still degrade (the read
clobbers r0..r14, so a later re-halt/resume is messy) - the intended
flow is power-on -> one halt -> dump.
Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
François
cdbeea7b61