François
c77d86efd0
New modules/svf/ plays the single-device SVF subset over the bscan_* primitives: SIR/SDR with masked TDO compare, RUNTEST (TCK/SEC), STATE (RESET/IDLE), ENDIR/ENDDR (IDLE only), HIR/HDR/TIR/TDR (length 0), TRST, FREQUENCY. Exposed as `svf_play <file>`. It warms up the FTDI link first — the MPSSE's first data read after open returns stale FIFO content, normally hidden because jtag_scan runs before anything. Also adds the bscan_tap_reset prototype. Validated on the live IGLOO2 M2GL010T: a hand-written IDCODE-check SVF passes (masked compare) and a deliberately wrong one is caught at the mismatching bit. A generic program dispatch off the prog tag, multi-device chains and non-IDLE end states are still TODO. Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
73 lines
3.0 KiB
C
73 lines
3.0 KiB
C
#ifndef _BSCAN_H
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#define _BSCAN_H
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/*
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* Single-device JTAG primitives and BSCAN-proxy operations.
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*
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* Provides:
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* - low-level JTAG TAP primitives (set_ir, shift_ir, shift_dr,
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* idle_cycles, tap_reset) that operate directly on jc->io_functions,
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* leaving jtag_core untouched. These are the building blocks the SVF
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* player and the proxy paths share;
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* - bitstream loading via CFG_IN to install a BSCAN proxy in the FPGA
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* fabric (Xilinx);
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* - a fast SPI transfer routine via USER1 once the proxy is loaded.
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*
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* (Was modules/bscan_spi/ — renamed once it grew past the SPI bridge
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* into general TAP primitives.)
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*
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* Current assumption: single device on the JTAG chain. Multi-device
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* support requires knowing the IR length of bypassed devices; defer.
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*/
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#include <stddef.h>
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#include <stdint.h>
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#include "jtag_core/jtag_core.h"
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#include "fpga/fpga.h"
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/* --- Low-level primitives (single-device chain) -------------------- */
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/* Shift `opcode` into IR. `ir_length` is the IR width in bits. */
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int bscan_set_ir(jtag_core *jc, unsigned int opcode, int ir_length);
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/* Shift `nbits` through DR. `tdi` may be NULL (shifts zeros).
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* `tdo` may be NULL (write only). Both buffers are LSB-first per byte. */
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int bscan_shift_dr(jtag_core *jc, const uint8_t *tdi, uint8_t *tdo, int nbits);
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/* Like bscan_shift_dr but through Shift-IR — a general IR scan with TDO
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* capture (bscan_set_ir is opcode-only). Single-device chain; buffers
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* LSB-first per byte. Both ends in Run-Test/Idle. */
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int bscan_shift_ir(jtag_core *jc, const uint8_t *tdi, uint8_t *tdo, int nbits);
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/* Emit `ncycles` TCK cycles while staying in Run-Test/Idle. */
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int bscan_idle_cycles(jtag_core *jc, int ncycles);
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/* Force Test-Logic-Reset (5 TCK with TMS=1) and land in Run-Test/Idle. */
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int bscan_tap_reset(jtag_core *jc);
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/* --- High-level operations ---------------------------------------- */
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/* Load a raw bitstream payload (no .bit container header) into the
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* FPGA via JPROGRAM -> CFG_IN -> shift -> JSTART. Bit-reverses each
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* byte before shifting (Xilinx convention). */
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int bscan_load_bitstream(jtag_core *jc, const fpga_target *t,
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const uint8_t *data, size_t nbytes);
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/* Convenience wrapper: read a file and load it. Detects the Xilinx
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* .bit header and skips it; otherwise treats the file as raw payload. */
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int bscan_load_bitstream_file(jtag_core *jc, const fpga_target *t,
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const char *path);
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/* One CS-framed SPI transaction through the BSCAN proxy (USER1 DR):
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* clock out `txlen` MOSI bytes (e.g. command + address + write data),
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* then read `rxlen` MISO bytes into `rx`. Either length may be 0.
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* Bytes are MSB-first on the wire; bit-order juggling is internal.
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* Follows the quartiq/OpenOCD jtagspi proxy framing. Single-device
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* chain only. Requires a proxy bitstream already loaded (USER1 live). */
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int bscan_spi_xfer(jtag_core *jc, const fpga_target *t,
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const uint8_t *tx, size_t txlen,
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uint8_t *rx, size_t rxlen);
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#endif
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