Files
bs_explorer/probes.yaml
François 3aad5e2308 jtag: driver-neutral JTAG_TCK_FREQ_KHZ clock (phase A)
One clock knob across probes instead of per-driver names:
- jtag_open mirrors JTAG_TCK_FREQ_KHZ into PROBE_FTDI_TCK_FREQ_KHZ for
  the Viveris FTDI driver (read-only at init); unset leaves the existing
  value untouched
- the Digilent driver reads JTAG_TCK_FREQ_KHZ directly instead of
  hardcoding 4 MHz (falls back to 4 MHz when unset)
- documented in probes.yaml; CLAUDE.md design note marks phase A done

FTDI path validated on the IGLOO2/FlashPro (250 kHz, mirror confirmed);
Digilent path not hardware-tested.

Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
2026-05-24 11:39:14 +02:00

32 lines
1.3 KiB
YAML

# bs_explorer probe-config profiles
#
# Loaded at runtime by modules/probes/, layered on top of the built-in
# config.script defaults. Looked up CWD-relative (run from the repo
# root), or via $BS_PROBES.
#
# defaults: applied on every `jtag_open` (restores a known baseline
# so opening without a profile is deterministic).
# profiles: named override sets; select with `jtag_open <idx> <name>`.
#
# Each key is a probe variable (see modules/config/config.script for the
# full list); each value is what `set <KEY> <value>` would assign.
defaults:
# Baseline for a standalone FT2232H JTAG probe: drive ADBUS4 as the
# "JTAG buffer enable" output (matches the built-in default).
PROBE_FTDI_SET_PIN_DIR_ADBUS4: 1
# Driver-neutral JTAG clock in kHz. Honoured by the FTDI driver (mapped
# to PROBE_FTDI_TCK_FREQ_KHZ at open) and our Digilent driver. Leave it
# out to keep each driver's own default (FTDI 1000, Digilent 4000).
# JTAG_TCK_FREQ_KHZ: 1000
profiles:
# Embedded FlashPro on Microsemi eval kits (FT4232H, JTAG on channel A
# = probe index 0). Its ADBUS4 must be left high-Z or the chain stays
# silent. Usage: jtag_open 0 flashpro
flashpro:
PROBE_FTDI_SET_PIN_DIR_ADBUS4: 0
# Plain FT2232H probe: nothing to override beyond the defaults.
ft2232h: {}