francois
545fe09fd5
modules/fpga/ holds an fpga_target struct (IDCODE/mask, family, IR length and private opcodes, proxy bitstream path, quirks) and a compile-time registry. Initial entry: Xilinx Kintex UltraScale+ XCKU15P, populated from bsdl_files/xcku15p_ffve1517.bsd (IDCODE 0x04A56093, IR 6, USER1=0x02, CFG_IN=0x05, JPROGRAM=0x0B, JSTART=0x0C, JSHUTDOWN=0x0D, ISC_DISABLE=0x16, quirk CCLK_VIA_STARTUP). Two new script commands: - fpga_list: enumerate the registry - fpga_info: match each device on the JTAG chain against the registry and surface known quirks Adding another FPGA = one entry in fpga_registry[] + its .bsd in bsdl_files/. Proxy .bit will be wired in phase 2.5 (bscan_spi/). Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
58 lines
1.9 KiB
C
58 lines
1.9 KiB
C
#ifndef _FPGA_H
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#define _FPGA_H
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/*
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* Per-target FPGA descriptor and registry.
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*
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* Holds the facts that cannot be derived from the BSDL alone:
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* - IDCODE pattern to match on the chain
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* - private IR opcodes (USER1, CFG_IN, JPROGRAM, …) needed for
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* configuration and for the BSCAN proxy bridge (Phase 2.5)
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* - path to the BSCAN proxy bitstream
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* - per-target quirks
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*
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* Adding an FPGA = one entry in fpga_registry[] + its .bsd in
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* bsdl_files/ + (optionally) its proxy .bit in bscan_proxies/.
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*/
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#include "jtag_core/jtag_core.h"
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typedef enum {
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FPGA_FAMILY_UNKNOWN = 0,
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FPGA_FAMILY_XILINX_7,
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FPGA_FAMILY_XILINX_US,
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FPGA_FAMILY_XILINX_USP,
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} fpga_family;
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/* Quirk flags */
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#define FPGA_QUIRK_CCLK_VIA_STARTUP (1u << 0) /* CCLK not directly drivable in EXTEST */
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typedef struct {
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const char *name; /* human-readable part name */
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unsigned long idcode; /* IDCODE pattern */
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unsigned long idcode_mask; /* bits to ignore (typically 0x0FFFFFFF for Xilinx — version masked) */
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fpga_family family;
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const char *bsdl_filename; /* basename within bsdl_files/ */
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int ir_length; /* IR width in bits */
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/* Private IR opcodes (0 = N/A for this family).
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* For Xilinx, these are read from the BSDL INSTRUCTION_OPCODE block. */
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unsigned int ir_cfg_in;
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unsigned int ir_user1;
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unsigned int ir_jprogram;
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unsigned int ir_jstart;
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unsigned int ir_jshutdown;
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unsigned int ir_isc_disable;
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const char *proxy_bitstream; /* path under bscan_proxies/, NULL if not yet available */
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unsigned int quirks;
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} fpga_target;
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/* Registry access */
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int fpga_get_target_count(void);
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const fpga_target * fpga_get_target_by_index(int index);
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const fpga_target * fpga_lookup_by_idcode(unsigned long idcode);
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const char * fpga_family_name(fpga_family f);
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#endif
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