francois
545fe09fd5
modules/fpga/ holds an fpga_target struct (IDCODE/mask, family, IR length and private opcodes, proxy bitstream path, quirks) and a compile-time registry. Initial entry: Xilinx Kintex UltraScale+ XCKU15P, populated from bsdl_files/xcku15p_ffve1517.bsd (IDCODE 0x04A56093, IR 6, USER1=0x02, CFG_IN=0x05, JPROGRAM=0x0B, JSTART=0x0C, JSHUTDOWN=0x0D, ISC_DISABLE=0x16, quirk CCLK_VIA_STARTUP). Two new script commands: - fpga_list: enumerate the registry - fpga_info: match each device on the JTAG chain against the registry and surface known quirks Adding another FPGA = one entry in fpga_registry[] + its .bsd in bsdl_files/. Proxy .bit will be wired in phase 2.5 (bscan_spi/). Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
8 lines
171 B
CMake
8 lines
171 B
CMake
set(SOURCE_DIR "${CMAKE_CURRENT_SOURCE_DIR}")
|
|
|
|
file(GLOB_RECURSE ALL_SOURCES "*.c")
|
|
|
|
include_directories(${CMAKE_CURRENT_SOURCE_DIR}/..)
|
|
|
|
add_library(fpga ${ALL_SOURCES})
|