francois
545fe09fd5
modules/fpga/ holds an fpga_target struct (IDCODE/mask, family, IR length and private opcodes, proxy bitstream path, quirks) and a compile-time registry. Initial entry: Xilinx Kintex UltraScale+ XCKU15P, populated from bsdl_files/xcku15p_ffve1517.bsd (IDCODE 0x04A56093, IR 6, USER1=0x02, CFG_IN=0x05, JPROGRAM=0x0B, JSTART=0x0C, JSHUTDOWN=0x0D, ISC_DISABLE=0x16, quirk CCLK_VIA_STARTUP). Two new script commands: - fpga_list: enumerate the registry - fpga_info: match each device on the JTAG chain against the registry and surface known quirks Adding another FPGA = one entry in fpga_registry[] + its .bsd in bsdl_files/. Proxy .bit will be wired in phase 2.5 (bscan_spi/). Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
65 lines
1.8 KiB
C
65 lines
1.8 KiB
C
#include <stddef.h>
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#include "fpga.h"
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static const fpga_target fpga_registry[] = {
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/* Xilinx Kintex UltraScale+ XCKU15P
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* IDCODE_REGISTER and INSTRUCTION_OPCODE values come from
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* bsdl_files/xcku15p_ffve1517.bsd
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* IR length 6 bits, version nibble (bits 31:28) ignored. */
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{
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.name = "Xilinx Kintex UltraScale+ XCKU15P",
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.idcode = 0x04A56093,
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.idcode_mask = 0x0FFFFFFF,
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.family = FPGA_FAMILY_XILINX_USP,
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.bsdl_filename = "xcku15p_ffve1517.bsd",
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.ir_length = 6,
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.ir_cfg_in = 0x05,
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.ir_user1 = 0x02,
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.ir_jprogram = 0x0B,
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.ir_jstart = 0x0C,
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.ir_jshutdown = 0x0D,
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.ir_isc_disable = 0x16,
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.proxy_bitstream = NULL, /* TODO Phase 2.5: bscan_spi_xcku15p.bit */
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.quirks = FPGA_QUIRK_CCLK_VIA_STARTUP,
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},
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};
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#define FPGA_REGISTRY_LEN ((int)(sizeof(fpga_registry) / sizeof(fpga_registry[0])))
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int fpga_get_target_count(void)
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{
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return FPGA_REGISTRY_LEN;
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}
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const fpga_target *fpga_get_target_by_index(int index)
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{
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if (index < 0 || index >= FPGA_REGISTRY_LEN) {
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return NULL;
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}
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return &fpga_registry[index];
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}
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const fpga_target *fpga_lookup_by_idcode(unsigned long idcode)
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{
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int i;
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for (i = 0; i < FPGA_REGISTRY_LEN; i++) {
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const fpga_target *t = &fpga_registry[i];
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if ((idcode & t->idcode_mask) == (t->idcode & t->idcode_mask)) {
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return t;
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}
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}
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return NULL;
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}
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const char *fpga_family_name(fpga_family f)
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{
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switch (f) {
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case FPGA_FAMILY_XILINX_7: return "Xilinx 7-Series";
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case FPGA_FAMILY_XILINX_US: return "Xilinx UltraScale";
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case FPGA_FAMILY_XILINX_USP: return "Xilinx UltraScale+";
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case FPGA_FAMILY_UNKNOWN:
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default: return "Unknown";
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}
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}
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