# bs_explorer FPGA registry
#
# Loaded at runtime by modules/fpga/. Looked up relative to the current
# directory (run bs_explorer from the repo root), or via $BS_FPGA_REGISTRY.
#
# One entry per programmable device. Fields:
#   name              human-readable part name (quoted)
#   idcode            JTAG IDCODE pattern (hex)
#   idcode_mask       bits compared when matching (0x0FFFFFFF on Xilinx
#                     masks the version nibble); default 0xFFFFFFFF
#   family            xilinx_7 | xilinx_us | xilinx_usp |
#                     microsemi_igloo2 | microsemi_smartfusion2 |
#                     lattice_machxo2 | lattice_machxo3
#   bsdl              basename of the .bsd in bsdl_files/
#   ir_length         IR width in bits
#   ir_cfg_in / ir_user1 / ir_jprogram / ir_jstart / ir_jshutdown /
#   ir_isc_disable    private IR opcodes (hex; from the BSDL on Xilinx)
#   proxy_bitstream   basename of the proxy .bit in bscan_proxies/
#                     (omit if none is available yet)
#   caveats           space/comma-separated flags: cclk_via_startup
#                     (omit if none)
#   max_tck_khz       max safe JTAG TCK in kHz for this part/board; if the
#                     requested clock exceeds it, jtag_autoinit clamps and
#                     re-opens at the cap (omit / 0 = unspecified)
#   prog              programming backend: proxy_spi | svf | none. Omit to
#                     infer (proxy_bitstream -> proxy_spi; Microsemi/Lattice
#                     -> svf; else none).

fpgas:
  # Xilinx Kintex UltraScale+ XCKU15P
  # IDCODE / opcodes from bsdl_files/xcku15p_ffve1517.bsd, IR length 6.
  - name:           "Xilinx Kintex UltraScale+ XCKU15P"
    idcode:         0x04A56093
    idcode_mask:    0x0FFFFFFF
    family:         xilinx_usp
    bsdl:           xcku15p_ffve1517.bsd
    ir_length:      6
    ir_cfg_in:      0x05
    ir_user1:       0x02
    ir_jprogram:    0x0B
    ir_jstart:      0x0C
    ir_jshutdown:   0x0D
    ir_isc_disable: 0x16
    caveats:        cclk_via_startup
    prog:           proxy_spi
    # proxy_bitstream not yet built for this part (see doc/tutorial.md, Phase 2.5)

  # Xilinx Kintex UltraScale XCKU040 (KCU105 eval board)
  # IDCODE / opcodes from bsdl_files/xcku040_ffva1156.bsd, IR length 6.
  - name:            "Xilinx Kintex UltraScale XCKU040"
    idcode:          0x03822093
    idcode_mask:     0x0FFFFFFF
    family:          xilinx_us
    bsdl:            xcku040_ffva1156.bsd
    ir_length:       6
    ir_cfg_in:       0x05
    ir_user1:        0x02
    ir_jprogram:     0x0B
    ir_jstart:       0x0C
    ir_jshutdown:    0x0D
    ir_isc_disable:  0x16
    proxy_bitstream: bscan_spi_xcku040.bit
    caveats:         cclk_via_startup
    prog:            proxy_spi

  # Microsemi IGLOO2 M2GL010T (M2GL-EVAL-KIT)
  # IDCODE / IR length from bsdl_files/m2gl010t-fg484.bsd
  #   IDCODE_REGISTER "XXXX1111100000000011000111001111" -> 0x0F8031CF
  #   (top nibble = silicon revision, masked off). Shared die with the
  #   SmartFusion2 M2S010, so both report the same IDCODE.
  # No proxy: IGLOO2 internal flash is programmed by playing an SVF
  # exported from Libero (SVF player not yet implemented), not via the
  # Xilinx BSCAN-proxy SPI path — so the ir_*/proxy fields don't apply.
  - name:           "Microsemi IGLOO2 M2GL010T"
    idcode:         0x0F8031CF
    idcode_mask:    0x0FFFFFFF
    family:         microsemi_igloo2
    bsdl:           m2gl010t-fg484.bsd
    ir_length:      8
    prog:           svf