bs_explorer

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Author	SHA1	Message	Date
François	71b74fa03d	fpga: rename "quirk" to "caveat" "quirk" was unclear jargon; "caveat" matches the wording already used in the README/CLAUDE.md ("Xilinx caveats"). Renames the struct field, the FPGA_QUIRK_* macro, the fpga_info output and the docs. No behaviour change.	2026-05-24 00:31:47 +02:00
François	ba9372c8b2	fpga: add XCKU040 (KCU105) registry entry IDCODE 0x03822093, UltraScale, opcodes from xcku040_ffva1156.bsd (same as the family: USER1 0x02, CFG_IN 0x05, JPROGRAM 0x0B, JSTART 0x0C). Points proxy_bitstream at bscan_spi_xcku040.bit.	2026-05-23 17:16:19 +02:00
francois	545fe09fd5	phase 2: add fpga/ module — per-target descriptor & registry modules/fpga/ holds an fpga_target struct (IDCODE/mask, family, IR length and private opcodes, proxy bitstream path, quirks) and a compile-time registry. Initial entry: Xilinx Kintex UltraScale+ XCKU15P, populated from bsdl_files/xcku15p_ffve1517.bsd (IDCODE 0x04A56093, IR 6, USER1=0x02, CFG_IN=0x05, JPROGRAM=0x0B, JSTART=0x0C, JSHUTDOWN=0x0D, ISC_DISABLE=0x16, quirk CCLK_VIA_STARTUP). Two new script commands: - fpga_list: enumerate the registry - fpga_info: match each device on the JTAG chain against the registry and surface known quirks Adding another FPGA = one entry in fpga_registry[] + its .bsd in bsdl_files/. Proxy .bit will be wired in phase 2.5 (bscan_spi/). Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>	2026-05-20 22:52:52 +02:00

Author

SHA1

Message

Date

François

71b74fa03d

fpga: rename "quirk" to "caveat"

"quirk" was unclear jargon; "caveat" matches the wording already used in
the README/CLAUDE.md ("Xilinx caveats"). Renames the struct field, the
FPGA_QUIRK_* macro, the fpga_info output and the docs. No behaviour
change.

2026-05-24 00:31:47 +02:00

François

ba9372c8b2

fpga: add XCKU040 (KCU105) registry entry

IDCODE 0x03822093, UltraScale, opcodes from xcku040_ffva1156.bsd
(same as the family: USER1 0x02, CFG_IN 0x05, JPROGRAM 0x0B,
JSTART 0x0C). Points proxy_bitstream at bscan_spi_xcku040.bit.

2026-05-23 17:16:19 +02:00

francois

545fe09fd5

phase 2: add fpga/ module — per-target descriptor & registry

modules/fpga/ holds an fpga_target struct (IDCODE/mask, family, IR
length and private opcodes, proxy bitstream path, quirks) and a
compile-time registry. Initial entry: Xilinx Kintex UltraScale+
XCKU15P, populated from bsdl_files/xcku15p_ffve1517.bsd (IDCODE
0x04A56093, IR 6, USER1=0x02, CFG_IN=0x05, JPROGRAM=0x0B, JSTART=0x0C,
JSHUTDOWN=0x0D, ISC_DISABLE=0x16, quirk CCLK_VIA_STARTUP).

Two new script commands:
- fpga_list: enumerate the registry
- fpga_info: match each device on the JTAG chain against the registry
  and surface known quirks

Adding another FPGA = one entry in fpga_registry[] + its .bsd in
bsdl_files/. Proxy .bit will be wired in phase 2.5 (bscan_spi/).

Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>

2026-05-20 22:52:52 +02:00

3 Commits