jtag: cap the clock by device max_tck_khz at autoinit (phase B)

- fpga_target gains max_tck_khz (registry key), the max safe JTAG TCK
  for a part/board (0 = unspecified)
- jtag_autoinit, after identifying the chain, resolves the clock: if the
  requested JTAG_TCK_FREQ_KHZ exceeds the smallest device max, it clamps
  it and re-opens the probe once (stored probe id) to apply, then
  re-scans; within-cap / unset just report the cap
- autoinit body extracted into autoinit_run() so it can re-run after the
  re-tune; fpga_list shows maxtck

Validated on the IGLOO2/FlashPro (req 500 -> clamp 200 -> reopen -> still
detected; within-cap and unset paths don't reopen).

Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>

modules/fpga/fpga.c

@@ -89,6 +89,7 @@ static void set_field(fpga_target *t, const char *key, const char *val)
     else if (!strcmp(key, "ir_isc_disable"))  t->ir_isc_disable = (unsigned int)strtoul(val, NULL, 0);
     else if (!strcmp(key, "proxy_bitstream")) { free((void *)t->proxy_bitstream); t->proxy_bitstream = xstrdup(val); }
     else if (!strcmp(key, "caveats"))         t->caveats        = parse_caveats(val);
+    else if (!strcmp(key, "max_tck_khz"))     t->max_tck_khz    = (int)strtol(val, NULL, 0);
     else fprintf(stderr, "fpga: unknown key '%s'\n", key);
 }
 

modules/fpga/fpga.h

@@ -52,6 +52,7 @@ typedef struct {
 
     const char    *proxy_bitstream;  /* path under bscan_proxies/, NULL if not yet available */
     unsigned int   caveats;          /* FPGA_CAVEAT_* flags */
+    int            max_tck_khz;      /* max safe JTAG TCK for this part/board, 0 = unspecified */
 } fpga_target;
 
 /* Registry access. The YAML file is loaded lazily on first call to any