target: generalize the registry to FPGAs + CPUs, add program dispatch

Restructure in anticipation of programming ARM CPUs (ARM7/9 via
EmbeddedICE, e.g. over an Olimex ARM-USB-OCD); FPGA path unchanged.

- modules/fpga -> modules/target; fpga_target -> jtag_target with a
  `kind` (fpga|cpu) and grouped fpga/cpu sub-structs; data/targets.yaml
  (env BS_TARGETS); API target_*; commands target_list/target_info
  (kind-aware). Add arm7/arm9 families, arm_flash prog, embeddedice
  debug, and cpu fields (ram_base/size, flash_base/size).
- new program/: `program <dev> <file>` dispatches by the target's prog
  (svf wired; proxy_spi points at the flash workflow; arm_flash -> arm_debug).
- new arm_debug/: EmbeddedICE halt/resume/mem + arm_flash backend
  declared, not implemented yet.
- bscan_* take const jtag_target* and read the fpga sub-struct.
- data/probes.yaml: arm-usb-ocd profile slot; data/targets.yaml: an ARM7
  example entry. Docs + an ARM-debug design note in CLAUDE.md.

Builds; FPGA path re-validated on the IGLOO2 (target_list shows the CPU
example; jtag_open/autoinit/program 0 <svf> all work).

Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>

src/modules/arm_debug/arm_debug.c

@@ -0,0 +1,56 @@
+#include <stdio.h>
+
+#include "arm_debug.h"
+
+/* Not implemented yet — every entry point reports failure for now. The
+ * real work — EmbeddedICE scan chains, halt/resume, memory access over
+ * the bscan_* primitives, and a per-MCU RAM flash loader — slots in
+ * behind these signatures without touching callers. */
+
+int arm_debug_halt(jtag_core *jc, const jtag_target *t)
+{
+    (void)jc; (void)t;
+    fprintf(stderr, "arm_debug: halt not implemented yet\n");
+    return -1;
+}
+
+int arm_debug_resume(jtag_core *jc, const jtag_target *t)
+{
+    (void)jc; (void)t;
+    fprintf(stderr, "arm_debug: resume not implemented yet\n");
+    return -1;
+}
+
+int arm_debug_mem_read(jtag_core *jc, const jtag_target *t,
+                       unsigned long addr, void *buf, unsigned long len)
+{
+    (void)jc; (void)t; (void)addr; (void)buf; (void)len;
+    fprintf(stderr, "arm_debug: mem_read not implemented yet\n");
+    return -1;
+}
+
+int arm_debug_mem_write(jtag_core *jc, const jtag_target *t,
+                        unsigned long addr, const void *buf, unsigned long len)
+{
+    (void)jc; (void)t; (void)addr; (void)buf; (void)len;
+    fprintf(stderr, "arm_debug: mem_write not implemented yet\n");
+    return -1;
+}
+
+int arm_flash_program(jtag_core *jc, const jtag_target *t, const char *file,
+                      arm_log_fn log, void *user)
+{
+    char msg[256];
+    (void)jc; (void)file;
+    if (log) {
+        snprintf(msg, sizeof(msg),
+            "arm_flash: backend not implemented yet. "
+            "Target '%s' debug=%d ram=0x%lX+0x%lX flash=0x%lX+0x%lX.",
+            t ? t->name : "?",
+            t ? (int)t->cpu.debug : 0,
+            t ? t->cpu.ram_base : 0UL, t ? t->cpu.ram_size : 0UL,
+            t ? t->cpu.flash_base : 0UL, t ? t->cpu.flash_size : 0UL);
+        log(user, 1, msg);
+    }
+    return -1;
+}