target: generalize the registry to FPGAs + CPUs, add program dispatch

Restructure in anticipation of programming ARM CPUs (ARM7/9 via
EmbeddedICE, e.g. over an Olimex ARM-USB-OCD); FPGA path unchanged.

- modules/fpga -> modules/target; fpga_target -> jtag_target with a
  `kind` (fpga|cpu) and grouped fpga/cpu sub-structs; data/targets.yaml
  (env BS_TARGETS); API target_*; commands target_list/target_info
  (kind-aware). Add arm7/arm9 families, arm_flash prog, embeddedice
  debug, and cpu fields (ram_base/size, flash_base/size).
- new program/: `program <dev> <file>` dispatches by the target's prog
  (svf wired; proxy_spi points at the flash workflow; arm_flash -> arm_debug).
- new arm_debug/: EmbeddedICE halt/resume/mem + arm_flash backend
  declared, not implemented yet.
- bscan_* take const jtag_target* and read the fpga sub-struct.
- data/probes.yaml: arm-usb-ocd profile slot; data/targets.yaml: an ARM7
  example entry. Docs + an ARM-debug design note in CLAUDE.md.

Builds; FPGA path re-validated on the IGLOO2 (target_list shows the CPU
example; jtag_open/autoinit/program 0 <svf> all work).

Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>

README.md

@@ -18,16 +18,18 @@ library by Viveris (LGPL).
 - JTAG chain detection through FTDI / J-Link / Linux GPIO / Digilent SMT2 probes: OK
 - Automatic BSDL loading by IDCODE: OK
 - Pin control in SAMPLE / EXTEST, incl. slow SPI bit-bang: OK
-- FPGA registry (runtime YAML: IDCODE → BSDL, IR opcodes, proxy, caveats, programming method): OK
+- Target registry (runtime YAML, FPGAs + CPUs: IDCODE → BSDL/debug, IR opcodes, proxy, caveats, programming method): OK
 - Probe-config profiles (`data/probes.yaml`) + driver-neutral JTAG clock with per-device cap: OK
 - BSCAN proxy SPI bridge (load proxy bitstream, talk SPI via `USER1`): OK
 - SPI flash detect / read / erase / program / verify: OK (~100 KB/s via the proxy)
 - SVF player (`svf_play`) — program any device from a vendor-exported SVF: OK (single-device subset)
+- `program <dev> <file>` — dispatches to the right backend by the target's `prog` method: OK
+- ARM7/9 CPU flashing (EmbeddedICE, ARM-USB-OCD): structure in place; debug/flash backend not implemented yet
 
 Bundled BSDLs: Xilinx Kintex UltraScale+ KU15P
 (`xcku15p_ffve1517.bsd`), Kintex UltraScale KU040 (`xcku040_ffva1156.bsd`),
 and Microsemi IGLOO2 M2GL010T (`m2gl010t-fg484.bsd`). Add more by dropping
-`.bsd` files in `data/bsdl_files/` plus an entry in `data/fpga_registry.yaml` (see
+`.bsd` files in `data/bsdl_files/` plus an entry in `data/targets.yaml` (see
 [`doc/tutorial.md`](doc/tutorial.md) for adding a target).
 
 ## Dependencies
@@ -76,8 +78,8 @@ are looked up relative to the current directory:
   full list. Loaded at startup.
 - `data/probes.yaml` — probe-config profiles, applied with
   `jtag_open <idx> <profile>` (`$BS_PROBES` overrides the path).
-- `data/fpga_registry.yaml` — the FPGA target registry
-  (`$BS_FPGA_REGISTRY` overrides the path).
+- `data/targets.yaml` — the FPGA target registry
+  (`$BS_TARGETS` overrides the path).
 - `data/bsdl_files/`, `data/bscan_proxies/` — BSDLs and proxy bitstreams.
 
 ## REPL
@@ -100,7 +102,7 @@ bs_explorer> jtag_profiles               # available profiles
 bs_explorer> jtag_open 0                 # or: jtag_open 0 <profile>
 
 # 2. Scan the chain and auto-load matching BSDLs
-bs_explorer> jtag_autoinit               # fpga_info then shows the prog method
+bs_explorer> jtag_autoinit               # target_info then shows the prog method
 
 # 3. Load the BSCAN proxy into the fabric (fast SPI bridge)
 bs_explorer> bscan_load_bitstream 0 data/bscan_proxies/bscan_spi_xcku040.bit
@@ -132,10 +134,10 @@ lives in [`doc/tutorial.md`](doc/tutorial.md).
 | Probe / chain | `jtag_probes`, `jtag_open`, `jtag_close`, `jtag_profiles`, `jtag_scan`, `jtag_autoinit`, `jtag_ndev`, `jtag_devices` |
 | BSDL / pins | `jtag_bsdl`, `jtag_pins`, `jtag_mode`, `jtag_pin_dir`, `jtag_pin_set`, `jtag_pin_get`, `jtag_push_pop` |
 | I²C / MDIO / SPI over BS pins (EXTEST) | `jtag_i2c_scl`, `jtag_i2c_sda`, `jtag_i2c_rd`, `jtag_i2c_wr`, `jtag_mdio_mdc`, `jtag_mdio_io`, `jtag_mdio_rd`, `jtag_mdio_wr`, `jtag_spi_cs/mosi/miso/clk`, `jtag_spi_xfer` |
-| FPGA registry | `fpga_list`, `fpga_info` |
+| Targets (FPGA/CPU) | `target_list`, `target_info` |
 | BSCAN proxy | `bscan_load_bitstream`, `bscan_jedec`, `bscan_set_ir`, `bscan_shift_dr` |
 | SPI flash (via proxy) | `flash_detect`, `flash_read`, `flash_erase`, `flash_write`, `flash_verify` |
-| SVF player | `svf_play` |
+| Program | `program` (dispatch by target), `svf_play` |
 | Misc | `help`, `?`, `version`, `exit` |
 
 Use `help <command>` for per-command help.
@@ -148,6 +150,8 @@ Use `help <command>` for per-command help.
   Microsemi eval kits, which needs ADBUS4 left high-Z) are handled by a
   **probe profile** in `data/probes.yaml`: `jtag_profiles` lists them,
   `jtag_open <idx> <profile>` applies one (e.g. `jtag_open 0 flashpro`).
+  The Olimex **ARM-USB-OCD** (also an FT2232, for ARM CPU targets) has an
+  `arm-usb-ocd` profile slot — pending its control-pin map.
 - **SEGGER J-Link**
 - **Linux GPIO** (sysfs; deprecated on recent kernels, libgpiod migration TBD)
 - **Digilent JTAG-SMT2 / SMT2-NC** — built in by default on Linux
@@ -166,7 +170,7 @@ flash on these parts.
 
 The **BSCAN proxy sidesteps this entirely**: it drives `CCLK` from the
 fabric internally, so flashing runs at full speed. Parts affected are
-flagged with the `CCLK_VIA_STARTUP` caveat in the registry (`fpga_info`
+flagged with the `CCLK_VIA_STARTUP` caveat in the registry (`target_info`
 shows it).
 
 ## Repository layout
@@ -180,17 +184,19 @@ src/                   — code + libs —
     ├── bsdl_parser/   .bsd loader
     ├── bus_over_jtag/ SPI / I²C / MDIO / parallel mem bit-bang (EXTEST)
     ├── drivers/       FTDI, J-Link, Linux GPIO, LPT, Digilent (optional)
-    ├── fpga/          Registry loader (parses data/fpga_registry.yaml at runtime)
+    ├── target/        Target registry loader: FPGAs + CPUs (data/targets.yaml)
     ├── bscan/         JTAG TAP primitives + BSCAN proxy (bitstream, SPI-over-USER1)
     ├── spi_flash/     SPI NOR chip database + read/erase/program/verify
     ├── svf/           SVF player (program from a vendor-exported SVF)
     ├── probes/        Probe-config profiles loader (data/probes.yaml)
+    ├── program/       `program` dispatch: routes a target to its backend by prog
+    ├── arm_debug/     ARM (EmbeddedICE) debug + flash backend (not implemented yet)
     ├── script/        Script engine
     ├── config/        Built-in config.script
     ├── os_interface/  Portable fs/network wrappers
     └── natsort/       Natural-order pin-name sorting
 data/                  — runtime resources, looked up from the CWD —
-├── fpga_registry.yaml FPGA registry (IDCODE → BSDL, IR opcodes, proxy, caveats)
+├── targets.yaml       Target registry (FPGAs + CPUs)
 ├── probes.yaml        Probe-config profiles (defaults + per-probe overrides)
 ├── bsdl_files/        BSDL files for target FPGAs
 ├── bscan_proxies/     BSCAN proxy bitstreams (MIT, from quartiq)