doc: reframe programming-backends note around a universal SVF player
Capture the vision: a single SVF player is a near-universal backend (Xilinx fabric config, Lattice, Microsemi IGLOO2, Altera, CPLDs from vendor-exported files); native backends are exceptions where streaming/ speed/control matter — chiefly Xilinx external SPI flash via the proxy. Adds a per-target path table and what an SVF player must implement.
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CLAUDE.md
103
CLAUDE.md
@@ -121,68 +121,65 @@ The FPGA must be in a configurable state before loading the proxy.
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Issue `JPROGRAM` first to reset, then `CFG_IN` + shift the bitstream,
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Issue `JPROGRAM` first to reset, then `CFG_IN` + shift the bitstream,
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then `JSTART` and check `DONE`.
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then `JSTART` and check `DONE`.
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## Extending to other FPGA families (design note)
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## Programming backends: beyond Xilinx external flash (design note)
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Not yet implemented — captured here so the design is ready when needed.
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Not yet implemented — captured so the design is ready. Guiding vision:
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Targets in mind: small Lattice MachXO2/MachXO3 (PSU sequencing/glue) and
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**one generic SVF player as a near-universal backend, with native
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Microsemi/Microchip IGLOO2 / SmartFusion2.
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backends only where streaming / speed / control justify them.**
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**Key difference from Xilinx.** Our Xilinx path programs an *external*
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### Why two layers
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SPI flash via a BSCAN proxy bitstream. Both Lattice MachXO2/3 and
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Microsemi IGLOO2 instead hold their config in *internal* flash,
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programmed *directly over JTAG* — no external flash, no proxy. So
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`bscan_spi/` and `spi_flash/` do **not** apply to them; they need a
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different programming backend.
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**What already generalises (reuse as-is):**
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Practically every JTAG-programmable device (Xilinx fabric config,
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- probe drivers, `jtag_core`, and the `bscan_set_ir` / `bscan_shift_dr`
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Lattice MachXO2/3, Microsemi IGLOO2/SmartFusion2, Altera, CPLDs, …) can
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primitives in `bscan_spi/` — vendor-neutral, and exactly what any
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be programmed from an **SVF** file exported by its vendor tool. SVF is a
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JTAG programming sequence drives;
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flat list of `SIR`/`SDR`/`RUNTEST` ops with the vendor's algorithm
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- IDCODE detection + BSDL load (BSDL is a standard);
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already baked in — so a single SVF player, built on our existing
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- the `fpga_target` registry concept and the script-command framework.
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`bscan_set_ir` / `bscan_shift_dr` primitives, programs almost anything
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with no per-vendor algorithm code.
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**Two strategies for the programming backend:**
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Native backends are the *exception*, justified only when you want fine
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control, speed, or no vendor-export step. Our Xilinx **external SPI
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flash** path is the prime example and stays native: load the BSCAN proxy
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once, then stream raw binary with separate read/erase/program/verify,
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progress and partial ops. The equivalent SVF ("indirect flash") is huge
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(tens of MB of ASCII) and inflexible.
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1. **Native per-family backend.** Implement the vendor's JTAG flow on
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### Where each path applies
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top of our IR/DR primitives.
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- *Lattice MachXO2/3*: the IEEE 1532 / ISC sequence — `ISC_ENABLE` →
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`ISC_ERASE` → `LSC_INIT_ADDRESS` → `LSC_PROG_INCR_NV` (page loop) →
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`ISC_PROGRAM_DONE`, with BUSY polling. Well documented (Lattice
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TN1204, IEEE 1532 BSDL `ISC_*` attributes) → very feasible. Needs a
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`.jed` parser for the payload.
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- *Microsemi IGLOO2*: the on-chip programming algorithm is
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proprietary and complex (sys-services, eNVM/fabric) — reimplementing
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it natively is a large, fragile effort. Not recommended.
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2. **Generic SVF / STAPL player (higher leverage).** Execute the JTAG
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| Target | Recommended path |
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programming file the vendor tool exports, instead of re-deriving the
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|--------|------------------|
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algorithm. The vendor's algorithm is *baked into the file*.
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| Xilinx external SPI config flash | **native proxy** (`bscan_spi/`+`spi_flash/`, done). SVF works but is bloated. |
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- **SVF** = a flat list of `SIR`/`SDR`/`RUNTEST` ops → a small player
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| Xilinx fabric config (volatile) | SVF, or our `bscan_load_bitstream` (equivalent) |
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on `bscan_set_ir`/`bscan_shift_dr` covers it; vendor-neutral
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| Lattice MachXO2/3 (internal flash) | **SVF** (Diamond/Radiant export). Native IEEE-1532 ISC optional, only for a self-contained `.jed` flow. |
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(Lattice, Microsemi, Altera all export SVF).
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| Microsemi IGLOO2 / SmartFusion2 | **SVF/STAPL** (Libero/FlashPro export). Native algorithm too complex/proprietary. |
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- **STAPL** (`.stp`/`.jam`) = a full language (loops, conditionals) →
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| Altera, CPLDs, misc JTAG | SVF |
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needs an interpreter, more work, but it's Microsemi's/Lattice's
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native portable format.
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- **For IGLOO2 this is the pragmatic route**: let Libero/FlashPro
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export SVF (or STAPL) and just play it. One player → many vendors.
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Recommendation: an **SVF player** is the single highest-value
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### The SVF player (the real work)
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addition — it unlocks IGLOO2 *and* most other JTAG parts at once,
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with the vendor owning the algorithm. Add native Lattice ISC only if
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a self-contained `.jed` flow (no vendor export step) is wanted.
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**Registry / dispatch adjustments:**
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A player is more than shifting bits. It must handle:
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1. `fpga_target` is Xilinx-flavoured today (`ir_cfg_in`, `ir_user1`,
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- `SIR`/`SDR` with `TDI`/`TDO`/`MASK` — the **masked TDO compare** is
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`ir_jprogram`, …). Generalise it — per-family opcode sets, or a small
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what detects prog/erase failures; that's the main addition over
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"programming method" tag (`proxy_spi` / `lattice_isc` / `svf`) that
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today's primitives;
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selects the backend.
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- `RUNTEST` delays (erase/program waits, in TCK or time) → reuse
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2. The existing `family` enum is the natural dispatch point
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`bscan_idle_cycles` + a sleep;
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(`FPGA_FAMILY_XILINX_*`, add `FPGA_FAMILY_LATTICE_*`,
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- `HIR/HDR/TIR/TDR` headers/trailers and `ENDIR/ENDDR/STATE` (multi-
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`FPGA_FAMILY_MICROSEMI_*`). An SVF player is family-agnostic and
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device chains, TAP state) — a standard subset covers ~all files.
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needs no per-part opcodes at all.
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**Scope caveat.** Lattice MachXO2/3 and IGLOO2/SmartFusion2 are genuinely
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It reuses probe drivers, `jtag_core`, `bscan_set_ir`/`bscan_shift_dr`
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JTAG-programmable. iCE40 is usually programmed over SPI directly (or
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and IDCODE/BSDL detection unchanged. **STAPL** (`.stp`/`.jam`) is the
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richer native format (a full language → needs an interpreter); more
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work, defer — do SVF first.
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### Registry / dispatch
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`fpga_target` is Xilinx-flavoured today (`ir_cfg_in`, `ir_user1`, …).
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Add a "programming method" tag (`proxy_spi` / `svf` / optional
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`lattice_isc`) selected off the `family` enum (add
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`FPGA_FAMILY_LATTICE_*`, `FPGA_FAMILY_MICROSEMI_*`). An SVF player is
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family-agnostic and needs no per-part opcodes — it can even run without
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a registry entry.
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**Scope caveat.** iCE40 is usually programmed over SPI directly (or
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one-time NVCM) with minimal JTAG — out of scope for this JTAG-centric
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one-time NVCM) with minimal JTAG — out of scope for this JTAG-centric
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tool.
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tool.
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