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fpga: rename "quirk" to "caveat"

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"quirk" was unclear jargon; "caveat" matches the wording already used in
the README/CLAUDE.md ("Xilinx caveats"). Renames the struct field, the
FPGA_QUIRK_* macro, the fpga_info output and the docs. No behaviour
change.
This commit is contained in:
Foué
2026-05-24 00:31:47 +02:00
parent 35b2022362
commit 71b74fa03d
5 changed files with 16 additions and 16 deletions
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8
doc/tutorial.md
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@@ -97,7 +97,7 @@ compile-time registry in `modules/fpga/fpga.c`:
```
bs_explorer> fpga_info
Device 0 IDCODE 0x04A56093 -> Xilinx Kintex UltraScale+ XCKU15P [Xilinx UltraScale+]
quirk: CCLK routed via STARTUP primitive (not drivable in EXTEST)
caveat: CCLK routed via STARTUP primitive (not drivable in EXTEST)
```
If you get `not in registry`, add an entry — see
@@ -146,7 +146,7 @@ Pin names depend on the board: dump `jtag_pins 0` to discover
them. On Xilinx FPGAs, the SPI flash is typically wired to the
configuration bank (e.g. `D00_MOSI_0`, `D01_DIN_0`, `FCS_B_0`) —
**except** `CCLK`, which goes through the `STARTUPE3` primitive and is
not drivable in EXTEST (the `CCLK_VIA_STARTUP` quirk on the target).
not drivable in EXTEST (the `CCLK_VIA_STARTUP` caveat on the target).
Send the JEDEC ID command (`0x9F` + 3 dummy bytes):
@@ -183,8 +183,8 @@ For an FPGA that's not in the registry yet:
3. **Add an entry** to `fpga_registry[]` in `modules/fpga/fpga.c`,
mirroring the existing KU15P entry. Set `proxy_bitstream` to
`NULL` for now; wire it up when you have one. Set quirks as
appropriate (e.g. `FPGA_QUIRK_CCLK_VIA_STARTUP` for any
`NULL` for now; wire it up when you have one. Set caveats as
appropriate (e.g. `FPGA_CAVEAT_CCLK_VIA_STARTUP` for any
Xilinx 7-Series/UltraScale/UltraScale+).
4. **Rebuild**. The registry is compile-time, no runtime registration.