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arm_debug: fix stale c1_xfer comment (bscan, not Pause-DR)

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The c1_ctx/c1_xfer comments still described the abandoned Pause-DR
parking model; the access is a single bscan_shift_dr (one debug clock
per access). Comment-only.

Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
This commit is contained in:
Foué
2026-05-24 18:28:55 +02:00
parent fda6aed077
commit 68229339e9
1 changed files with 12 additions and 16 deletions
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28
src/modules/arm_debug/arm_debug.c
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@@ -184,30 +184,26 @@ int arm_debug_resume(jtag_core *jc, const jtag_target *t)
return 0;
}
/* Scan-chain-1 (debug bus) access session. Mirrors OpenOCD's TAP usage:
* accesses are parked in Pause-DR so each injected instruction is clocked
* by exactly one Update-DR. Crucially we never dwell in Run-Test/Idle,
* which would generate extra debug clocks and desync the core's
* instruction pipeline (the bscan_* primitives all pass through Idle, so
* they can't be reused here). The Update for access N is emitted at the
* start of access N+1; c1_end() flushes the final pending Update.
* Captured data reflects the value the core drives on the bus when the
* access samples it at Capture-DR — the standard ARM7TDMI debug pipeline
* that the NOP padding in read/write_core_regs accounts for. */
/* Scan-chain-1 (debug bus) access session. Each access is one
* bscan_shift_dr of the 33-bit frame, which captures the bus at
* Capture-DR, applies the instruction at Update-DR and advances the core
* exactly one debug step (Update -> Run-Test/Idle) — one access == one
* debug clock. The captured value reflects the bus from the previous
* step's instruction, the standard ARM7TDMI pipeline that the NOP padding
* in read/write_core_regs accounts for. (c1_init/c1_end bracket a run of
* accesses; c1_end is currently a no-op since bscan_shift_dr self-completes
* each access, but callers must still avoid chain switches mid-run — those
* clock the halted core and shift the pipeline phase.) */
typedef struct {
jtag_core *jc;
int started; /* a scan is currently parked in Pause-DR */
int started;
} c1_ctx;
static void c1_init(c1_ctx *c, jtag_core *jc) { c->jc = jc; c->started = 0; }
/* One chain-1 access: shift 33 bits = breakpoint[0] | flip32(instr)[1..32].
* sysspeed=1 marks the following instruction to run at system speed.
* capture != NULL reads back the 32-bit debug data bus.
* Parks in Pause-DR so each instruction is clocked by exactly ONE
* Update-DR (no Run-Test/Idle dwell, which would add debug clocks). The
* Update for access N is emitted at the start of access N+1; c1_end()
* flushes the final one. */
* capture != NULL reads back the 32-bit debug data bus. */
static int c1_xfer(c1_ctx *c, uint32_t instr, int sysspeed, uint32_t *capture)
{
uint8_t buf[5], cap[5];