fpga: load registry from yaml at runtime, not compile-time

- registry moves from the array in fpga.c to fpga_registry.yaml at the
  repo root, parsed via libyaml (pkg-config yaml-0.1); adding a part is
  now a YAML edit, no rebuild
- looked up CWD-relative (like bsdl_files/), overridable with
  $BS_FPGA_REGISTRY, loaded lazily once; public API unchanged
- fpga_list shows the source file (fpga_registry_source())
- add microsemi_igloo2/smartfusion2 and lattice_machxo2/3 families,
  ready for the non-Xilinx targets
- docs updated: CLAUDE.md, README, tutorial "add a target" walkthrough

Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>

README.md

@@ -28,6 +28,8 @@ target).
 
 - CMake ≥ 3.10, gcc/clang
 - `readline` (Arch: `readline`, Debian/Ubuntu: `libreadline-dev`)
+- `libyaml` for the FPGA registry, found via pkg-config `yaml-0.1`
+  (Arch: `libyaml`, Debian/Ubuntu: `libyaml-dev`)
 - `libftd2xx` for FTDI probes (vendored in `libs/libftd2xx/`)
 - *To drive a Digilent SMT2/SMT2-NC probe:* the Digilent
   [Adept Runtime](https://digilent.com/shop/software/digilent-adept/)
@@ -149,13 +151,14 @@ modules/
 ├── bsdl_parser/     .bsd loader
 ├── bus_over_jtag/   SPI / I²C / MDIO / parallel mem bit-bang (EXTEST)
 ├── drivers/         FTDI, J-Link, Linux GPIO, LPT, Digilent (optional)
-├── fpga/            Per-target registry (IDCODE, BSDL, IR opcodes, caveats)
+├── fpga/            Registry loader (parses fpga_registry.yaml at runtime)
 ├── bscan_spi/       BSCAN proxy loader + fast SPI-over-USER1 bridge
 ├── spi_flash/       SPI NOR chip database + read/erase/program/verify
 ├── script/          Script engine
 ├── config/          Built-in config.script
 ├── os_interface/    Portable fs/network wrappers
 └── natsort/         Natural-order pin-name sorting
+fpga_registry.yaml   FPGA registry (IDCODE → BSDL, IR opcodes, proxy, caveats)
 bsdl_files/          BSDL files for target FPGAs
 bscan_proxies/       BSCAN proxy bitstreams (MIT, from quartiq)
 scripts/             Example scripts