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jtag/fpga: prog method tag + RTCK link setting (phase C)

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- fpga_target gains a prog method (proxy_spi/svf/none), set in the
  registry or inferred when omitted (proxy_bitstream -> proxy_spi;
  Microsemi/Lattice -> svf); shown by fpga_info/fpga_list and exposed via
  fpga_prog_method_name() for the future program dispatch
- generalise RTCK as a neutral JTAG_RTCK, mirrored to
  PROBE_FTDI_JTAG_ENABLE_RTCK at open (FTDI-only)
- reset abstraction deferred (no clean neutral form yet); the program
  dispatch command itself lands with the SVF player

Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
This commit is contained in:
Foué
2026-05-24 11:53:02 +02:00
parent ac883237ac
commit 2a03cb1145
5 changed files with 74 additions and 5 deletions
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15
modules/script/script.c
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@@ -1960,6 +1960,15 @@ static int cmd_open_probe(script_ctx *ctx, char *line)
}
}
// Driver-neutral adaptive clock (JTAG_RTCK, 0/1): mirror to the FTDI
// driver's variable when explicitly set (0 is meaningful, so test
// presence rather than value). FTDI-only; no Digilent equivalent.
{
char rtck[32];
if (getEnvVarDat((envvar_entry *)ctx->env, "JTAG_RTCK", rtck, sizeof(rtck)))
setEnvVarDat((envvar_entry *)ctx->env, "PROBE_FTDI_JTAG_ENABLE_RTCK", rtck);
}
ret = jtagcore_select_and_open_probe(jc, id);
if (ret != JTAG_CORE_NO_ERROR)
{
@@ -2994,10 +3003,10 @@ static int cmd_fpga_list(script_ctx *ctx, char *line)
i, t->idcode, t->idcode_mask,
t->name, fpga_family_name(t->family));
ctx->script_printf(ctx, MSG_NONE,
" bsdl=%s ir=%d proxy=%s caveats=0x%x maxtck=%dkHz\n",
" bsdl=%s ir=%d proxy=%s caveats=0x%x maxtck=%dkHz prog=%s\n",
t->bsdl_filename, t->ir_length,
t->proxy_bitstream ? t->proxy_bitstream : "(none yet)",
t->caveats, t->max_tck_khz);
t->caveats, t->max_tck_khz, fpga_prog_method_name(t->prog));
}
return JTAG_CORE_NO_ERROR;
}
@@ -3030,6 +3039,8 @@ static int cmd_fpga_info(script_ctx *ctx, char *line)
ctx->script_printf(ctx, MSG_INFO_0,
"Device %d IDCODE 0x%.8lX -> %s [%s]\n",
i, idcode, t->name, fpga_family_name(t->family));
ctx->script_printf(ctx, MSG_NONE,
" prog: %s\n", fpga_prog_method_name(t->prog));
if (t->caveats & FPGA_CAVEAT_CCLK_VIA_STARTUP) {
ctx->script_printf(ctx, MSG_NONE,
" caveat: CCLK routed via STARTUP primitive (not drivable in EXTEST)\n");