jtag/fpga: prog method tag + RTCK link setting (phase C)
- fpga_target gains a prog method (proxy_spi/svf/none), set in the registry or inferred when omitted (proxy_bitstream -> proxy_spi; Microsemi/Lattice -> svf); shown by fpga_info/fpga_list and exposed via fpga_prog_method_name() for the future program dispatch - generalise RTCK as a neutral JTAG_RTCK, mirrored to PROBE_FTDI_JTAG_ENABLE_RTCK at open (FTDI-only) - reset abstraction deferred (no clean neutral form yet); the program dispatch command itself lands with the SVF player Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
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@@ -30,6 +30,13 @@ typedef enum {
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FPGA_FAMILY_LATTICE_MACHXO3,
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} fpga_family;
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/* Programming method — which backend drives this part. */
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typedef enum {
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FPGA_PROG_NONE = 0, /* no known method */
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FPGA_PROG_PROXY_SPI, /* Xilinx external SPI flash via the BSCAN proxy */
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FPGA_PROG_SVF, /* play a vendor-exported SVF (Lattice/Microsemi/…) */
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} fpga_prog_method;
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/* Caveat flags: known hardware gotchas for a part. */
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#define FPGA_CAVEAT_CCLK_VIA_STARTUP (1u << 0) /* CCLK not directly drivable in EXTEST */
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@@ -53,6 +60,7 @@ typedef struct {
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const char *proxy_bitstream; /* path under bscan_proxies/, NULL if not yet available */
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unsigned int caveats; /* FPGA_CAVEAT_* flags */
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int max_tck_khz; /* max safe JTAG TCK for this part/board, 0 = unspecified */
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fpga_prog_method prog; /* programming backend; inferred when omitted */
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} fpga_target;
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/* Registry access. The YAML file is loaded lazily on first call to any
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@@ -61,6 +69,7 @@ int fpga_get_target_count(void);
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const fpga_target * fpga_get_target_by_index(int index);
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const fpga_target * fpga_lookup_by_idcode(unsigned long idcode);
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const char * fpga_family_name(fpga_family f);
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const char * fpga_prog_method_name(fpga_prog_method m);
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/* Path the registry was loaded from, or NULL if nothing loaded
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* (file missing / parse error). For diagnostics. */
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