jtag/fpga: prog method tag + RTCK link setting (phase C)

- fpga_target gains a prog method (proxy_spi/svf/none), set in the
  registry or inferred when omitted (proxy_bitstream -> proxy_spi;
  Microsemi/Lattice -> svf); shown by fpga_info/fpga_list and exposed via
  fpga_prog_method_name() for the future program dispatch
- generalise RTCK as a neutral JTAG_RTCK, mirrored to
  PROBE_FTDI_JTAG_ENABLE_RTCK at open (FTDI-only)
- reset abstraction deferred (no clean neutral form yet); the program
  dispatch command itself lands with the SVF player

Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>

CLAUDE.md

@@ -194,8 +194,14 @@ fact bounded by both the probe and the board/device.
   apply, then re-scans. Within-cap / unset just report the cap. Effective
   `tck = min(request, device max)`; probe-max (`min(..., probe max)`) is
   still TODO.
-- **C** — generalise the other link settings (reset/RTCK) and wire the
-  `prog` method tag into backend dispatch (ties into the SVF player).
+- **C (done)** — `prog` method tag (`proxy_spi`/`svf`/`none`) on each
+  registry entry, inferred when omitted (proxy → `proxy_spi`; Microsemi/
+  Lattice → `svf`); shown by `fpga_info`/`fpga_list` and available via
+  `fpga_prog_method_name()` for backend dispatch. RTCK generalised as a
+  neutral `JTAG_RTCK` (mirrored to `PROBE_FTDI_JTAG_ENABLE_RTCK`,
+  FTDI-only). Reset abstraction deferred — it's a bundle of probe-
+  specific pin/polarity/timing vars with no clean neutral form yet. The
+  actual `program` dispatch command lands with the SVF player.
 
 What exists already: the **probe layer** (`probes.yaml`) and the
 **device layer** (`fpga_registry.yaml`). The new work is the **JTAG-link