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added tutorial for creating an additional spi proxy for Xilinx.

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Foué
2026-05-26 14:52:40 +02:00
parent 39963fd6d8
commit 243c66f4c7
2 changed files with 180 additions and 15 deletions
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doc/tutorial.md
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@@ -353,24 +353,16 @@ The registry entry for the part points at this file via its
quartiq ships `.bit` only for the parts its generator knows — it has
**no UltraScale+** proxy (its single UltraScale entry is the KU040), so
the KU15P has to be built from source. You need (o)Migen + Vivado
(2022.2; ISE 14.7 for older parts). From a clone of the quartiq repo,
per its README:
anything in the UltraScale+ family (XCKU15P, XCKU3P, XCKU11P, XCZU…,
Virtex US+, …) has to be built from source. You need (o)Migen + Vivado
(2022.2 for UltraScale/+; ISE 14.7 only for Spartan-6 and earlier).
```sh
python3 -m venv --system-site-packages .venv
./.venv/bin/pip install -r requirements.txt
PATH=$PATH:/opt/Xilinx/Vivado/2022.2/bin \
./.venv/bin/python3 xilinx_bscan_spi.py ...
```
Step-by-step walkthrough in [doc/build_xilinx_proxy.md](build_xilinx_proxy.md),
worked out on the KU15P.
The XCKU15P first has to be **added to the generator's device table**
(a Migen platform entry) — it's not just a command-line part flag.
Once built, drop `bscan_spi_xcku15p.bit` into `data/bscan_proxies/` (it's
Once built, drop `bscan_spi_<part>.bit` into `data/bscan_proxies/` (it's
MIT, like the KU040 — keep `data/bscan_proxies/LICENSE.quartiq`) and set the
`proxy_bitstream` field on the KU15P entry in `data/targets.yaml`
(currently omitted).
`proxy_bitstream` field on the matching entry in `data/targets.yaml`.
### Load the bridge and talk SPI